An integrated system for developing regular array designs

Guo, Shaori; Luk, Wayne

doi:10.1016/s1383-7621(00)00052-7

Cited by 13 publications

(5 citation statements)

References 25 publications

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“…• a symbolic simulator based on the Rebecca system [14], which can simulate bit-level and word-level designs, and combine symbolic, numeric and logical inputs and outputs;…”

Section: Implementation: Maxeler Targetsmentioning

confidence: 99%

Verification of streaming designs by combining symbolic simulation and equivalence checking

Todman

Luk

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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As design complexity grows, verification becomes a bottleneck in design development and implementation. This paper describes a novel approach for verifying reconfigurable streaming designs, based on symbolic simulation and equivalence checking. Compared with numerical simulation, symbolic simulation provides a more informative way of showing a design behaved as expected; equivalence checking enables automatic checking of equivalence of symbolic expressions. Our approach has been implemented for designs targeting Maxeler technologies, using an easy-to-use symbolic simulator and the Yices equivalence checker, together with other facilities such as an output combiner to support an automated verification flow. Several benchmarks including, including one-dimensional convolution and finite difference computation, are used to evaluate the proposed approach.

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“…• a symbolic simulator based on the Rebecca system [14], which can simulate bit-level and word-level designs, and combine symbolic, numeric and logical inputs and outputs;…”

Section: Implementation: Maxeler Targetsmentioning

confidence: 99%

Verification of streaming designs by combining symbolic simulation and equivalence checking

Todman

Luk

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

Self Cite

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“…(ii) The Lava system [130] can convert designs into a form suitable for input to a model checker; a number of FPGA design libraries have been verified in this way [131]. (iii) The Ruby language [132] supports correctnesspreserving transformations, and a wide variety of hardware designs have been produced. (iv) The Pebble [133] hardware design language has been formally specified [134], so that provably-correct design tools can be developed.…”

Section: Emerging Directions 441 Verificationmentioning

confidence: 99%

Reconfigurable computing: architectures and design methods

Todman

Constantinides

Wilton

et al. 2005

IEE Proc., Comput. Digit. Tech.

276

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Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and specialpurpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.

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“…Our design is loosely based on a state-machine-based design that has been described by using the Ruby language [12]. Our realization differs because we are able to exploit the VHDL-style wiring connection support available in Quartz rather than being restricted to Ruby's variable-free notation; this makes the description simpler and closer to what most circuit designers are familiar with.…”

Section: Describing and Verifying Complete Circuitsmentioning

confidence: 99%

“…Systems based on Ruby [12] and Lava [7] have been used to exploit the geometric interpretation of higher-order combinators to generate placed circuits; however, both generate flattened netlists, not parametrized output. Hence, it is difficult to use these languages and tools to create parametrized library circuits that can be used in existing design flows.…”

Section: Related Workmentioning

confidence: 99%

Verification of FPGA Layout Generators in Higher-Order Logic

Pell

2006

J Autom Reasoning

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Manual placement of components is often used in FPGA circuit design in order to achieve better results than would be generated by automatic place and route algorithms. However, explicit placement of basic elements in parametrized hardware descriptions is tedious and error-prone. We describe a framework for the description and verification of parametrized hardware libraries with layout information, supporting both placing components with explicit symbolic coordinates and 'neighboring' placement directives such as A beside B. The correctness of generated layouts is established by proof in higher-order logic, automated by using the Isabelle theorem prover. We have developed an extensive library of theorems describing properties of layouts that are combined by our compiler and the theorem prover to achieve a high level of automation in the verification of complete circuit layouts, making formal verification of circuit layouts practical with minimal user effort. Our system has been used to verify layout descriptions for a range of circuits that have been mapped to Xilinx FPGAs.

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An integrated system for developing regular array designs

Cited by 13 publications

References 25 publications

Verification of streaming designs by combining symbolic simulation and equivalence checking

Verification of streaming designs by combining symbolic simulation and equivalence checking

Reconfigurable computing: architectures and design methods

Verification of FPGA Layout Generators in Higher-Order Logic

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