Abstract:A simple yet accurate interconnect parasitical capacitance model is presented. Based on this model a novel interconnect bus optimization methodology is proposed. Combining wire spacing with wire ordering, this methodology focuses on bus dynamic power optimization with consideration of bus performance requirements. The optimization methodology is verified under a 65 nm technology node and it shows that with 50% slack in the routing space, a 33.03% power saving can be provided by the proposed optimization method… Show more
An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering * Zhu Zhang-Ming(朱樟明) a)b) † , Hao Bao-Tian(郝报田) a) , En Yun-Fei(恩云飞) a)b) , Yang Yin-Tang(杨银堂) a) , and Li Yue-Jin(李跃进) a)
An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering * Zhu Zhang-Ming(朱樟明) a)b) † , Hao Bao-Tian(郝报田) a) , En Yun-Fei(恩云飞) a)b) , Yang Yin-Tang(杨银堂) a) , and Li Yue-Jin(李跃进) a)
According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed resistanceinductance-capacitance (RLC) interconnect considering effect of thermal profile. According to the 65-nm complementary metal-oxide semiconductor (CMOS) process, we compare the proposed RLC analytical crosstalk model with the Hspice simulation results for different interconnect coupling conditions and the absolute error is within 6.5%. The computed results of the proposed analytical crosstalk model show that RCL crosstalk decreases with the increase of current density and increases with the increase of insulator thickness. This analytical crosstalk model can be applied to the electronic design automation (EDA) and the design optimization for nanometer CMOS integrated circuits.
Power system inherently consists of capacitance and inductance in its components. Equipment with saturable inductance and circuit capacitance provides circumstances of generating ferroresonance, resulting in overvoltage and overcurrent in the connected system. The effects of ferroresonance result in insulation failure and hence damage to the equipment is unavoidable. Though many devices are proposed for mitigating such circumstances, a promising technology of using memristors may provide better performance than others in the future. A memristor emulator using the N-channel JFET J310 is used in this work. Unlike other electronic components that replicate memristor properties, the chosen memristor emulator is a passive device since it does not need any external power supply. Simulation and experimental results verify the design of a memristor emulator and the characteristics of an ideal memristor. Experimental results prove that the memristor emulator can suppress the fundamental ferroresonance induced in a prototype single phase transformer. The results of the harmonic analysis also validate the memristor performance against the conventional technique.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.