A continuous-time analog delay is designed as a requirement for the autocorrelation function in the Quadrature Downconversion Autocorrelation Receiver (QDAR) [1]. An eightorder Pade approximation of its transfer function is selected to implement this delay. Subsequently, the orthonormal form [1] is adopted, which is intrinsically semi-optimized for dynamic range, has low sensitivity to component mismatch, high sparsity and whose coefficients can be physically implemented. Each coefficient in the state-space description of the orthonormal ladder filter is implemented at circuit level using a novel 2-stage gm cell employing negative feedback. Simulation results in IBM's Bi-CMOS 0.12 pm technology show that this delay filter requires a total current of 70 mA at a 1.6 V power supply. The 1-dB compression point of the delay is at 565 mV and the SNR is 47.5 dB. On performing a Monte Carlo simulation it becomes evident that the response of the frequency selective analog delay does not suffer drastically from neither process variations nor component mismatch.