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This paper presents the system-level modeling of a Reconfigurable System on Chip (RSoC) that is being currently developed in our institution. Although there is a wide range of possible applications, our system is initially aiming fruit monitoring system. The proposed RSoC contains a 32-bit RISC microprocessor, reconfigurable structures, analog and digital interfaces, an RF transceiver and an Active Pixel Sensor (APS) matrix whose function will consist basically on image acquisition. The modeling at a high level of abstraction has been used lately in the design and verification of SoCs due to the rising complexity of such systems. Virtual platforms using SystemC description language at Transaction-Level Modeling (TLM) allow efficient simulations including software and hardware. In this work, a preliminary evaluation of a systemlevel description of the RSoC is carried out. A JPEG compression algorithm was mapped and implemented as a case study to test the accuracy of the model. Future implementations will include the description of an RF transceiver and the communication between two RSoCs.

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A class EF2 power oscillator designed in standard 130 nm CMOS at 2.5 GHz frequency is presented. The oscillator relies on a direct path based on a power amplifier and a feedback path based on passive elements and an MOS varactor. Class EF2 is used to reduce voltage stress across the switch, enabling a higher output power for modern transistors with low breakdown voltage. The measurement on a class EF2 power oscillator at radio frequency (RF) is presented for the first time. The circuit achieves 17.65 dBm output power from a 2.5 V supply voltage with 27.1% DC-RF efficiency and presents a 150 MHz tuning range. The measured phase noise is −101.6 dBc/Hz at 1 MHz offset. The circuit was implemented in standard 130 nm CMOS technology and consumed a total area of 1.95 mm 2. To the authors' knowledge this class EF2 power circuit has never been presented either at RF frequencies or in an integrated technology.