An investigation into the security of self-timed circuits

Yu, Zuoxia; Furber, Steve; Plana, Luis A.

doi:10.1109/async.2003.1199180

Cited by 34 publications

(19 citation statements)

References 34 publications

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“…Asynchronous logic gates can be used to lower Electromagnetic (EM) emission levels by reducing or eliminating the need for clock synchronization [56,57]. This technique can be used to mitigate the covert attacks: SPA, SEMA, DEMA, and DPA.…”

Section: Asynchronous Logic Gatesmentioning

confidence: 99%

“…Random noise can be employed to decrease the Signal-to-Noise Ratio (SNR) of IC signals [54], and make emissions more independent of the chip operations [53,55]. Chip emissions can also be masked using asynchronous logic gates [56,57], or reduced by using low power design techniques [53]. Further, emissions between chip regions can be lowered via design partitioning [20,21].…”

Section: Introductionmentioning

confidence: 99%

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Hardware Attack Mitigation Techniques Analysis

Moein¹,

Gulliver²,

Gebali³

et al. 2017

IJCIS

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Section: Asynchronous Logic Gatesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hardware Attack Mitigation Techniques Analysis

Moein¹,

Gulliver²,

Gebali³

et al. 2017

IJCIS

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show abstract

“…Special types of CMOS logic elements have been proposed in [2], but this low-level approach requires changing gate libraries and hence is costly for a standard cell or FPGA user. As a solution, using balanced data encoding such as dual-rail or together with self-timed design techniques has been proposed in [3,4].…”

Section: Introductionmentioning

confidence: 99%

Improving the Security of Dual-Rail Circuits

Sokolov

Murphy

Bystrov

et al. 2004

Lecture Notes in Computer Science

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Abstract. Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method.

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“…In this context, self-timed circuits seem an interesting alternative, since it is more difficult to correlate the leaking syndromes to the data flowing in a secure design in the absence of a global synchronization signal [4] [8].…”

Section: Introductionmentioning

confidence: 99%

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA

Lomne¹,

Maurine²,

Торрес³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind triple rail logic are valid and may provide interesting design guidelines to get DPA resistant circuits which are also more robust against DEMA.

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An investigation into the security of self-timed circuits

Abstract: Abstract

Cited by 34 publications

References 34 publications

Hardware Attack Mitigation Techniques Analysis

Hardware Attack Mitigation Techniques Analysis

Improving the Security of Dual-Rail Circuits

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA

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