Improving the Security of Dual-Rail Circuits

Abstract

Abstract. Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method.

A digital design flow for secure integrated circuits

“…3 (middle) and (left) shows the WDDL AOI32 gate with drive strength 2 and the original static CMOS gate. Compared with the use of negative differential logic, proposed in [25], the introduction of the inverters does not result in an area overhead. They act as buffers: while for a negative function, the transistors implementing the complex function must be made large, the drive strength now is provided by the inverters.…”

“…In [25], an alternating spacer protocol is proposed. Instead of always precharging to 0, the idea is to alternate precharging to 0 and precharging to 1.…”

An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications

“…Using the 1-of-encoding-which is a balanced data encoding-in association with the balanced FPGA architecture enhances the security characteristics of the FPGA and makes DPA attacks more difficult [31]. With this encoding style, both logical "0" and logical "1" are encoded with code words of the same Hamming weight, "01" and "10, " respectively.…”

Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints

“…The most relevant logic styles of this kind are SABL [18,19], WDDL [20], and Dual-Spacer DRP [16]. In these DRP logic styles, the signals are represented by two complementary wires.…”