An Investigation into Three-Level Ferroelectric Memory

Raiter, K.R.; Cockburn, B.F.

doi:10.1109/mtdt.2005.17

Cited by 2 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Raiter and Cockburn reported the possibility of using three data-signal levels to increase the array storage density from 1 bit per cell to 1.5 bits per cell by using three-level FeRAM. [ 10 ] When each cell of the FeRAM has three polarization states (named L, M, and H), nine states (LL, LM, LH, ML, MM, MH, HL, HM, and HH) can be programmed into two FeRAM cells. Therefore, if eight of nine possible states are used, two cells of the FeRAM can work as three cells of a traditional binary memory with the aid of peripheral circuitry.…”

Section: Introductionmentioning

confidence: 99%

Tristate Memory Using Ferroelectric-Insulator-Semiconductor Heterojunctions for 50% Increased Data Storage

et al. 2011

View full text Add to dashboard Cite

Ferroelectric random‐access memory (FeRAM) is considered to be one of the best candidates for universal memory. However, difficult scaling of the memory cell size has hindered the realization of high density FeRAM. Given that size scaling is inherently limited by the complicated crystal structure and processing of ferroelectric materials, the highly stable and step‐wise three memory state of one cell can be another pathway to high‐density FeRAM. A feasible structure and actual operation of a tristate memory function for high‐density FeRAM is presented that uses stacked ferroelectric Pb(Zr,Ti)O3/insulating Al2O3/semiconducting ZnO layers with Pt top and bottom electrodes. The complicated electrical responses of the stacked structure to external stimuli are well understood based on the separated trapping of the compensating charges at the Pb(Zr,Ti)O3/Al2O3 and Al2O3/ZnO interfaces and the discrete dissipation of the trapped charges during polarization switching in one direction. This unique function of the structure induces three discrete charge states that can be used to increase the memory density by 50% compared to conventional FeRAM at a given cell size.

show abstract

Section: Introductionmentioning

confidence: 99%

Tristate Memory Using Ferroelectric-Insulator-Semiconductor Heterojunctions for 50% Increased Data Storage

et al. 2011

View full text Add to dashboard Cite

show abstract

“…However, how to integrate such non-Si FETs on Si VLSIs is still a challenge. Figure 8.33(a) shows cell distributions for a ternary FeRAM [58] and (b) a 3b/cell NAND [59]. A multivalue storage cell is another topic of interest for smaller die or macro sizes.…”

Section: Circuit Challenges To Fatigue-free Operation or Nondestructimentioning

confidence: 99%

Embedded Memories for Nano-Scale VLSIs

2009

Integrated Circuits and Systems

View full text Add to dashboard Cite

An Investigation into Three-Level Ferroelectric Memory

Abstract: Ferroelectric random-access memory (FeRAM)

Cited by 2 publications

References 7 publications

Tristate Memory Using Ferroelectric-Insulator-Semiconductor Heterojunctions for 50% Increased Data Storage

Tristate Memory Using Ferroelectric-Insulator-Semiconductor Heterojunctions for 50% Increased Data Storage

Embedded Memories for Nano-Scale VLSIs

Contact Info

Product

Resources

About