An investigation of latency prediction for NoC-based communication architectures using machine learning techniques

Abstract

Due to the increasing number of cores in Systems on Chip (SoCs), bus architectures have suffered with limitations regarding performance. As applications demand higher bandwidth and lower latencies, buses have not been able to comply with such requirements due to longer wires and increased capacitance. Facing this scenario, Networks-on-Chip (NoCs) emerged as a way to overcome the limitations found in bus-based systems. Fully exploring all possible NoC characteristics settings is unfeasible due to the vast design space to cover. Therefore, some methods which aim to speed up the design process are needed. In this work, we propose the use of machine learning techniques to optimise NoC architecture components during the design phase. We have investigated the performance of several different ML techniques and selected the Random Forest one targeting audio/video applications. The results have shown an accuracy of up to 90% and 85% for prediction involving arbitration and routing protocols, respectively, and in terms of applications inference, audio/video achieved up to 99%. After this step, we have evaluated other classifiers for each application individually, aiming at finding the adequate one for each situation. The best class of classifiers found was the Tree-based one (Random Forest, Random Tree, and M5P) which is very encouraging and it points to different approaches from the current state of the art for NoCs latency prediction.

Multicriteria Deming Regressive African Buffalo Optimized Mapping for 3D NoC Architecture Design

“…But the framework failed to use an efficient evolutionary technique to minimize the convergence time. e machine learning techniques were introduced in [9] for designing the NoC architecture components.…”

Uma Ferramenta Baseada Em Inteligência Artificial Para Exploração De Espaço De Projeto Para Redes Em Chip / an Artificial Intelligence-Based Tool for Exploiting Design Space for Chip Networks

“…Frequency and channel bandwidth are defined as 100MHz and 3200Mbps, respectively. The simulations execute until all packets are delivered since each configuration could result in better or worse classifier accuracy.RedScarf simulator (daSilva et al, 2019) generates all instances with each simulation resulting in a different instance. RedScarf is a simulation environment targeting performance evaluation of NoCs models by simulating SystemC RTL descriptions.…”