An Investigation on Hot-Carrier Reliability and Degradation Index in Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors

Abstract

The hot-carrier-induced degradation in the high-voltage n-type lateral diffused metal-oxide-semiconductor (LDMOS) fieldeffect transistor is investigated. Interface state generation caused by hot-electron injection in the channel region is identified to be the main degradation mechanism. Since the gate current (I g ) consists mainly of the electron injection, I g correlates well with the hot-carrier lifetime of the device. The impact of varying device layout parameter on the performance and hot-carrier lifetime of the device are also evaluated. Such an analysis can achieve a better design of LDMOS transistors when considering both device performance and hot-carrier reliability.

Characteristics and reliability of metal–oxide–semiconductor transistors with various depths of plasma-induced Si recess structure

“…[24][25][26][27] Some other groups claimed that a higher V G value results in greater hot-carrier-induced device degradation. 28,29) Results in Fig. 7 reveal that the V G value at which the maximum hot-carrier-induced device degradation is produced is that at which the peak I sub is produced in our devices.…”

Investigation of characteristics and hot-carrier reliability of high-voltage MOS transistors with various doping concentrations in the drift region

“…For the device stressed under a fixed V D , one of the previous reports show that the V G value to produce the maximum hot-carrier induced device degradation is the V G value to produce the maximum of I sub [8]. Some other reports claimed that a higher V G value results in a greater hot-carrier induced device degradation [4,9]. Such apparent inconsistencies result from different device design and bias conditions used in past studies.…”

“…Because the devices are operated under high voltages, the off-state breakdown voltage is a key device parameter. Furthermore, hot-carrier induced device degradation, caused by the damage near the Si-SiO 2 interface and/or charge trapping in the gate oxide due to a high electric field near the drain end of the channel, is prone to developing into a serious reliability concern [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16]. For the design of n-type highvoltage MOS transistors, a lightly doped n − drift region next to the drain is usually employed to achieve the required breakdown voltage.…”