An Iterative Array for Multiplication of Signed Binary Numbers

Majithia, J.C.; Kitai, R.

doi:10.1109/t-c.1971.223216

Cited by 24 publications

(6 citation statements)

References 3 publications

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“…Sign bit for the first row = c.| + c cla (13) It may be noted that it is difficult to show the circuit-implementation of relation (12) in each row of Fig. 5.…”

Section: Ill Divider Array-like Structurementioning

confidence: 99%

Optimum array-like structures for high-speed arithmetic

Agrawal

1975

1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)

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I INTRODUCTIONArray-like structures for high-speed multiplication, division, square and square-root operations have been described in this paper. In these designs the division and square-rooting time have been made to approach to that of multiplication operation. These structures are optimum from speed and versatility point of view. Most of the cellular arrays described in the literature are adequately slow. The time delay is particularly significant in the division and square-rooting operations due to the ripple effect of the carries. Though the carry-save technique has been widely utilized for multiplication operation, it has been only recently employed by Cappa et.al. in the design of a nonrestoring divider array. This requires sign-bit detection that makes the array non-uniform. Such an array has been named as an array-like structure. The carrysave method has been extended here for restoring division operation. Due to sign-detection and overflow correction requirements, the restoring method is slightly complex. But the main advantage of such restoring array is in its simple extension for multiplication operation. The array for the two operations, when pipelined, will have more computing power than all other multiplier-divider arrays. Suggestions have also been included for further speed improvement.The technique applied for division operation is as well applicable for the square-rooting and an arraylike structure for square-square-rooting operations has also been given. For performing any one of the four operations, the only manipulation to be done is to combine the two arrays; one for multiplicationdivision and another for square-square-rooting. Possible methods of combining the two arrays have been indicated and their relative advantages and disadvantages have been mentioned. Finally, a generalized pipeline array-like structure with complete internal details and for 4-bit operation, has been shown. Due

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“…Sign bit for the first row = c.| + c cla (13) It may be noted that it is difficult to show the circuit-implementation of relation (12) in each row of Fig. 5.…”

Section: Ill Divider Array-like Structurementioning

confidence: 99%

Optimum array-like structures for high-speed arithmetic

Agrawal

1975

1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)

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“…Both methods yield multipliers with total delays that are proportional to the logarithm of the operand word-length, which is faster than array multipliers [6] or sequential multipliers (e.g., multipliers which implement Booth's algorithm [7]). As shown in [8], parallel Wallace and Dadda multipliers achieve optimal speed for both pipelined and non-pipelined implementations.…”

Section: Introductionmentioning

confidence: 99%

Parallel reduced area multipliers

Bickerstaff

Schulte

Swartzlander

1995

Journal of VLSI Signal Processing

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Abstract.As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction of the partial products. The reduction scheme can be applied to either unsigned (sign-magnitude) or two's complement numbers. Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead for Wallace, Dadda, and Reduced Area multipliers. Area estimates indicate that for non-pipelined multipliers, the reduction in area achieved with Reduced Area multipliers ranges from 3.7 to 6.6 percent relative to Dadda multipliers, and from 3.8 to 8.4 percent relative to Wallace multipliers. For fully pipelined multipliers, the reduction in area ranges from 15.1 to 33.6 percent relative to Dadda multipliers, and from 2.9 to 9.0 percent relative to Wallace multipliers.

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“…In fact, their layout can be automatically generated by iteratively A Recursive Algorithm for Binary Multiplication 295 reproducing the layout of a single cell on a plane. Using the same cells, networks for multiplying signed numbers were proposed [ 1,9,17] possessing the same area and time complexity. An extended review with interesting comments and contributions to the design of parallel multipliers can be found in the book by In order to increase the speed of iterative multipliers with time complexity O(N), some macrocellular structures have also been proposed.…”

Section: Introductionmentioning

confidence: 99%

A recursive algorithm for binary multiplication and its implementation

Mori

Cardin

1985

ACM Trans. Comput. Syst.

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A new recursive algorithm for deriving the layout of parallel multipliers is presented. Based on this algorithm, a network for performing multiplications of two's complement numbers is proposed. The network can be implemented in a synchronous or an asynchronous way. If the factors to be multiplied have N bits, the area complexity of the network is O(N') for practical values of N as in the case of cellular multipliers. Due to the design approach based on a recursive algorithm, a time complexity O(log N) is achieved.It is shown how the structure can he pipelined with period complexity O(1) and used for single and double precision multiplication.

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An Iterative Array for Multiplication of Signed Binary Numbers

Cited by 24 publications

References 3 publications

Optimum array-like structures for high-speed arithmetic

Optimum array-like structures for high-speed arithmetic

Parallel reduced area multipliers

A recursive algorithm for binary multiplication and its implementation

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