An NMOS test chip for a course in semiconductor parameter measurements

Abstract

This report describes an NMOS test chip, NBS-40, which was developed to be used in graduate level electronics engineering courses involving semiconductor parameter measurements associated with the fabrication of integrated circuits. The 35 test structures included in the test chip and their use in materials, device, and process parameter measurements are described. Details of the silicon gate NMOS process used in the chip fabrication are also provided.