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-NIST and Sandia have developed a procedure for producing and calibrating critical b:.g dimension (CD), or linewidth, reference materials. + These reference materials will be used to_ '% calibrate metrology instruments used in semiconductor manufacturing. The artifacts, with~w idths down to 100 nm, are produced in monocrystalline silicon with all feature edges aligned to specific crystal planes.A two-part calibration of these Iinewidths is used: the primary calibration, with accuracy to within a few lattice plane thicknesses, is accomplished by counting the lattice planes across the sample as-imaged through use of high-resolution transmission electron microscopy (HRTEM). The secondary calibration is the high-precision electrical CD technique.NIST and Sandia are developing critical dimension (CD), or .linewidth, reference materials for use by the semiconductor industry. To meet the current requirements of this rapidly changing industry, the widths of the reference features must be at or below the widths of the finest features in production and/or development.Further, these features must produce consistent results no matter which metrology tooI (e.g., scanning electron microscope, scanned probe microscope, electrical metrology) is used to make the measurement."~This leads to a requirement for the samples to have planar surfaces, known sidewall angles, and uniform material composition. None of the production techniques in use in semiconductor manufacturing can produce features with all these characteristics.In addition, requirements specified in the National Technology Roadmap for Semiconductors indicate that the width of the feature must be accurately calibrated to approximately 1-2 nm, a value well beyond the current capabilities of the instruments used for semiconductor metrology.Since current processes used for semiconductor device fabrication cannot produce features with these requirements, an approach utilizing features processed from monocrystalline silicon has been developed.4 Monocrystalline silicon allows for lattice-plane selective etch processing that produces features which are roughly aligned to the mask but are aligned exactly to the silicon : crystal lattice plane. These etch techniques, commonly associated with the processing of 'Contribution of the National Institute of Standards and Technology (NIST). Not subject to copyright.

A new, robust, high-sensitivity, electrical test structure based on the voltagedividingpotentiometer principle, and designed for the measurement of the separations of pairs of conducting features, has recently been reported [l]. In the earlier work, the uncorrected measurements had a systematic error in the hundreds of nanometers. However, after compensating for this error, the residual errors were typically as low as 15 nm. In later work, through further measurements and extensive modeling, the origin of the systematic error was attributed to substratedependent' asymmetries of certain imperfections in the replication of the test structure [2]. In this paper, modified test structures are described that confirm the model and show how all design-rule and substratedependent systematic errors can be eliminated. THREE CLASSES OF APPLICATION OF FEATURE PLACEMENT METROLOGYAmong the technological requirements for semiconductor manufacturing for the 1990s is overlaying successive patterns of material on the wafer with accuracy and precision in the low tens-of-nanometers range.Lithographic tools with such a capability are being developed, but the metrology to monitor and evaluate the performance of these new tools routinely is lagging. There are some advanced techniques such as electron beam and optical photon scattering image analysis that provide, at high cost, limited information which has value early in the tool and process development cycle. However, electrical test structures provide low-cost, post-patterning metrology for overlay that is routinely available during the advanced stages of process development and during manufacturing.There are three classes of applications for test structures in the measurement of overlay, and these are briefly reviewed in the following three subsections. The purpose of the review is to provide the reader with a background to demonstrate the advantages of the subject test structure. CLASS 1 APPLICATIONS: PRIMARY PATTERN GENERATION FEATURE PLACEMENT EVALUATIONIn primary pattern generation applications, the entire test structure is replicated in a single conducting film on the substrate after it is imaged by a steered beam and developed in an overlying resist film. The serial printing of the features of the test structure may be interrupted by a stage andlor field repositioning. The test structure allows the evaluation of the registration of the features printed prior to the interruption to those printed subsequently. CLASS 2 APPLICATIONS: MASK OVERLAY MEASUREMENTTwo different complementary patterns together constituting the test structure are exposed using the sume tool into the same single resist film prior to development of the composite image and its replication in an underlying conducting film. The test structure enables the determination of local discrepancies in the overlay of the two exposures. If both the exposures are made using masks, and the mask-induced contributions to I In this context the term "substratedependcnt" means that the error was constant for all teat StNCtIIres ...