An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise

Abstract

As the low-frequency noise of a transistor grows nonnegligible in advanced technologies, the possibility of using noise for computation is becoming an alternative, receiving more and more attention. The ability to control the noise level would further enrich the flexibility of the circuit design. Therefore, this letter presents a dual-gate field-effect transistor in an octagonal shape. By changing the voltage of an extra gate above the shallow trench isolation, the transistor is able to adapt its low-frequency noise over several decades and in a power-efficient manner. The octagonal geometry further makes sufficient a voltage range from 0 to 5 V for the noise adaptation. Moreover, the transistor is fabricated with the standard CMOS logic process without additional masks. All the features underpin the development of large-scale noisy computation in integrated circuits.Index Terms-Dual-gate transistor, low-frequency noise, noise adaptability, shallow trench isolation (STI).

Stochastic neuron design using conductive bridge RAM

“…It is possible to exploit the thermal noise in the CMOS but this may lead to silicon overheads and unwanted correlations [6]. Other techniques exploit CMOS circuits with using noise but have significant area overhead [13], or the noise of photons with photodetectors [14] or even special kinds of 'noisy transistors' [15]. Finally it was proposed to use fundamentally probabilistic nanodevices like single electron transistors [16], but which might suffer from poor CMOS compatibility and room temperature operation.…”

A Resist-Protection-Oxide Transistor With Adaptable Low-Frequency Noise for Stochastic Neuromorphic Computation in VLSI

“…However, these methods require extra process steps and simply boost the low-frequency noise to a usable extent without considering the noise adaptability. An octagonal dualgate transistor is thus proposed in [13], employing an extra gate on the shallow trench isolation (STI) to adapt the extra noise induced by the STI-silicon interface. This letter presents a resist-protection-oxide (RPO) fieldeffect transistor (FET) (Fig.…”

“…The noise level is adaptable by the drain voltage, based on the principle that the drain-side depletion would be able to screen off the RPO defects [14], analogous to the mechanism explored to achieve the multilevel flash memory [15]. This mechanism allows the RPO-FET to control the noise level directly with a relatively lower voltage than that required by the dual-gate transistor in [13]. In addition, the RPO-FET is fabricated with the standard CMOS 0.18-µm logic technology without additional masks or process steps, facilitating the integration with ordinary CMOS integrated circuits.…”