An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V

Sawada, Kazuaki; Sugawara, Yutaka; Masui, Shoichi

doi:10.1109/vlsic.1995.520692

Cited by 51 publications

(27 citation statements)

References 2 publications

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“…The clock generator proposed in this paper produces 4 phase clocks; each clock (CLK 1 , CLK 2 , CLK 3 , and CLK 4 ) has a certain fixed delay, unlike other references [9][10][11][12]16].…”

Section: Reconfigurable Charge Pump Architecturementioning

confidence: 99%

A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

Park¹,

Jang²,

Cho³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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“…The clock generator proposed in this paper produces 4 phase clocks; each clock (CLK 1 , CLK 2 , CLK 3 , and CLK 4 ) has a certain fixed delay, unlike other references [9][10][11][12]16].…”

Section: Reconfigurable Charge Pump Architecturementioning

confidence: 99%

A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

Park¹,

Jang²,

Cho³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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“…The Dickson charge pump [5,8,9] has a similar structure to the ladder topology in that it has two ladders of capacitors. However, in this topology, both ladders move with respect to ground.…”

Section: Dickson Charge Pumpmentioning

confidence: 99%

“…Thus, these transistors must be actively driven from circuits running at the MOSFET transistors'source potential. Several gate drive schemes have been developed for FLASH memory supplies [5,8,9]. Such a drive circuit is shown in figure 12.…”

Section: Gate Drive Techniquesmentioning

confidence: 99%

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Analytical and Practical Analysis of Switched-Capacitor DC-DC Converters

Seeman¹

2006

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Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. Switched-capacitor DC-DC converters are useful alternatives to inductor-based converters in many lowpower and medium-power applications. This work develops a straightforward analysis method to determine a switched-capacitor converter?s output impedance (a measure of performance and power loss). This resistive impedance is a function of frequency and has two asymptotic limits, one corresponding to very high switching frequency where resistive paths dominate the impedance, and one corresponding to very low switching frequency where charge transfers among idealized capacitors dominate the impedance. An optimization method is developed to improve the performance of these converters through component sizing based on practical constraints. Several switched-capacitor converter topologies are compared in the two asymptotic limits. Switched-capacitor converter performance (based on conduction loss) is compared with that of two magnetics-based DC-DC converters. At moderate to high conversion ratios, the switchedcapacitor converter has significantly less conduction loss than an inductor-based buck converter. Some aspects of converter implementation are discussed, including the power loss due to device parasitics and methods for transistor control. Implementation using both integrated and discrete devices is discussed. With the correct analysis methods, switched-capacitor DC-DC converters can provide an attractive alternative to conventional power converters. All rights reserved.Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Next comes my other grad student friends, especially the EEGSA folk, as they help me get out and socialize and occasionally enjoy a beer on someone else's buck. They're a fun bunch of (unfortunately) mostly guys who think that grad school is not all about work. And then there's Ankur, who has always entertained me while doing ME 233 problem sets or th...

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“…However, all Dickson-derived schemes [3], [4] suffer from a number of drawbacks. The main limit consists in large area occupation when a high number of stages in low-voltage fabrication processes is required.…”

Section: Introductionmentioning

confidence: 99%

Heap Charge Pump Optimisation by a Tapered Architecture

Arona

Bonizzoni

Maloberti

et al.

2005 IEEE International Symposium on Circuits and Systems

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-The heap charge pump represents an attractive voltage multiplier scheme in integrated circuits where only low-voltage devices are available. This paper presents a performance optimisation of the heap charge pump achieved by using a tapered architecture. The proposed optimisation allows improvements on the order of 30% in terms of maximum output voltage as compared to the conventional heap charge pump. A mathematical description of both the conventional and the proposed structure was developed. MATLAB ® -based simulation results demonstrate the effectiveness of the proposed scheme.

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An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V

Cited by 51 publications

References 2 publications

A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

Analytical and Practical Analysis of Switched-Capacitor DC-DC Converters

Heap Charge Pump Optimisation by a Tapered Architecture

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