Heap Charge Pump Optimisation by a Tapered Architecture

Abstract

-The heap charge pump represents an attractive voltage multiplier scheme in integrated circuits where only low-voltage devices are available. This paper presents a performance optimisation of the heap charge pump achieved by using a tapered architecture. The proposed optimisation allows improvements on the order of 30% in terms of maximum output voltage as compared to the conventional heap charge pump. A mathematical description of both the conventional and the proposed structure was developed. MATLAB ® -based simulation results demonstrate the effectiveness of the proposed scheme.

Analysis of Charge Pump Topologies for High Voltage Mobile Microphone Applications

“…Furthermore, for the Doubler topology, only half of the area was used to yield the area for the capacitors between stages [12]. In topologies, where capacitors are stacked, a higher voltage gain may be achieved by tapering of capacitor sizes [15], this has not been done in the calculations of this paper. Instead, each stage has been allocated an equal amount of area for pumping capacitors.…”

Modular Realization of Capacitive Converters Based on General Transposed Series–Parallel and Derived Topologies

“…The simple series-parallel (SP) topology, in which the capacitors are charged in parallel and discharged in series (or vice versa), belongs to that family. There are other capacitive-based converters, which have inherent principal losses due to the significant voltage difference on the capacitors in the various operating states [20], [21].…”

Linear distribution of capacitance in Dickson charge pumps to reduce rise time

“…In general, the capacitors of the CP are usually designed with equal size because this choice allows to maximize the output current, , but to optimize some CP features, there are very few cases which adopt different size for the stage capacitors . In particular, in Arona et al where the heap CP topology is considered, a tapered sizing is adopted to improve the maximum output voltage, while in Saeed et al, a sizing strategy for the stage capacitors of a Dickson CP is exploited to achieve benefits in terms of rise time.…”

“…In general, the capacitors of the CP are usually designed with equal size because this choice allows to maximize the output current, , but to optimize some CP features, there are very few cases which adopt different size for the stage capacitors . In particular, in Arona et al where the heap CP topology is considered, a tapered sizing is adopted to improve the maximum output voltage, while in Saeed et al, a sizing strategy for the stage capacitors of a Dickson CP is exploited to achieve benefits in terms of rise time. The methodology proposed in Saeed et al, which is surely interesting and opens a new way, has the drawback of proposing an unhandy algorithm for choosing each capacitor value, and, moreover, it is numerically solved only for CP with a number of stages, N , up to 6, while for memory application, a much higher number of stages is usually required…”

“…Thus, the adoption of a CP with a better rise time allows optimizing the silicon area.This research paper is inserted in this context and proposes a novel CP where, unlike the traditional approach, the pumping capacitors are differently sized to achieve a rise time reduction for a given silicon area occupation.In general, the capacitors of the CP are usually designed with equal size because this choice allows to maximize the output current, 1,12,13 but to optimize some CP features, there are very few cases which adopt different size for the stage capacitors. 14,15 In particular, in Arona et al 15 where the heap CP topology is considered, a tapered sizing is adopted to improve the maximum output voltage, while in Saeed et al, 14 a sizing strategy for the stage capacitors of a Dickson CP is exploited to achieve benefits in terms of rise time. The methodology proposed in Saeed et al, 14 which is surely interesting and opens a new way, has the drawback of proposing an unhandy algorithm for choosing each capacitor value,…”