An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

Abstract

There is, however, a finite probability that the circuit will not resolve its metastable state correctly within the allowed time.To enable assessing the risk, and to enable the design of reliable synchronizers and systems, models describing the failure mechanisms for latches and flip flops have been developedMost models express the risk of not resolving metastability in terms of the mean time between failures (MTBF) of the circuit (1).Where C F and D F are the receiver and sender frequencies, respectively, τ is the resolution time constant, and W T is a parameter often related to the setup-and-hold time window at the synchronizer input.Desirable values of MTBF depend on the application and range from several years upwards. The parameter τ is predominant in synchronizer characterization since its effect on MTBF is exponential. Hence lower values of τ correspond to a "good" synchronizer while higher values to a "bad" one.Typical values of τ are the same order of magnitude as the gate delay of the technology (often expressed as FO4, the fanout-of-four delay of a standard gate). Evidently, as technology scales, FC and FD increase and to maintain high MTBF (without increasing N) τ must decrease as well.In the past, τ was believed to improve with technology scaling [4]. However, recent measurements [5] [6] indicate that scaling trends of synchronizers should be re-considered: The need to obtain full characterization will be imperative in technologies beyond 45nm. This paper describes a fully digital on-chip characterization circuit to measure synchronization performance. Our work also compares different synchronization circuits and demonstrates that the standard library flip flop achieves better performance relative to other solutions. To demonstrate the system, a 102x78 2 m µ on-chip digital measurement circuit was fabricated in a low power 1.1V 65nm bulk CMOS process (Fig. 9). II PROPOSED CHARACTERIZATION METHODThe measurement consists of sampling the output of the FF-under-test twice: first (X in Fig 2a) by the clock delayed by a factor DL (by means of a delay line) and second (Y) by the negative edge of the clock. The two samples are compared by a XOR gate. A metastability event that resolves during the time window between the delayed and negative edges of the clock (namely an event that did not resolve within the allotted time S) increments the counter (the number of events expected to resolve after the negative edge of the clock is negligible, since a low frequency clock is used). The measurement continues for time period T and thus MTBF is T divided by the counter value.978-1-4244-9474-3/11/$26.00

A new 65nm LP metastability measurment test circuit

“…As a result, careful simulation of the system design at several points throughout its operating region combined with verification is proposed as a dependable approach to the detection of potential metastability failures. This paper describes a fully digital on-chip characterization circuit to measure synchronization performance that is an improvement of the circuit shown in [7]. We show a new calibration circuit to compare measurements and simulations over a wide range of supply voltage and temperature corners for a standard library flip flop.…”

An Extended Metastability Simulation Method for Synchronizer Characterization

“…All simulations were performed using SPICE BSIM4 model level 54. The measurement method was described in [ 11] A comparison of in measurements and simulations is presented graphically in Fig. 9 for different levels of supply voltage between 0.95V and 1.3V, at room temperature.…”

Variability in Multistage Synchronizers

“…Physical measurement of synchronizer characteristics is usually limited to the very first stage [2]- [4], because of the unbounded time required to carry out measurements on later synchronizer stages. Reliable simulation of the entire synchronizer is now possible, however, due to state-of-the-art simulation methods [15], and has been validated against first stage measurements [16].…”