An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

Herbst, Steven; Rutsch, Gabriel; Ecker, Wolfgang; Horowitz, Mark

doi:10.1109/tcad.2021.3102516

Cited by 8 publications

(2 citation statements)

References 21 publications

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“…MSDSL is a Python-based synthesizable module generator [28]. Its working principle involves translating the syntax rules of a high-level domain-specific language (DSL) into low-level DSL code.…”

Section: Electronic System Level Design Methodologymentioning

confidence: 99%

Python-Based Circuit Design for Fundamental Building Blocks of Spiking Neural Network

Qin

et al. 2023

Electronics

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Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the X variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips.

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Section: Electronic System Level Design Methodologymentioning

confidence: 99%

Python-Based Circuit Design for Fundamental Building Blocks of Spiking Neural Network

Qin

et al. 2023

Electronics

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“…This property guarantees that chains of blocks will compute a result within a given time step that determines the maximum sampling rate of the model. Further improvements in emulation performance have been explored by [11] using variable time steps to overcome the tradeoff between the emulator's throughput and the represented time resolution. The toolchain used for that approach uses designer-provided mathematical models of analog circuits to synthesize them with piecewise linear approximations.…”

Section: State Of the Artmentioning

confidence: 99%

Using High-Level Synthesis to model System Verilog procedural timing controls

Pozzoni,

Ferrandi,

Mendola

et al. 2023

2023 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In modern SoC designs, digital components' development and verification processes often depend on the component's interactions with other digital and analog modules on the same die. While designers can rely on a wide range of tools and practices for validating fully-digital models, porting the same workflow to mixed models' development requires significant efforts from the designers. A common practice is to use Real Number Modeling techniques to generate HDL-based behavioral models of analog components to efficiently simulate mixed models using only eventbased simulations rather than Analog Mixed Signals (AMS) simulations. However, some of these models' language features are not synthesizable with existing synthesis tools, requiring additional efforts from the designers to generate post-tapeout prototypes. This paper presents a methodology for transforming some non-synthesizable SystemVerilog language features related to timing controls into functionally-equivalent synthesizable Verilog constructs. The resulting synthesizable models replicate their respective RNMs' behavior while explicitly managing delay controls and event expressions. The RNMs are first transformed using the MLIR framework and then synthesized with open-source HLS tools to obtain FPGA-synthesizable Verilog models.

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