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Neural circuits must both execute the behavioral repertoire of individuals and account for behavioral variation across species. Understanding how this variation emerges over evolutionary time requires large-scale phylogenetic comparisons of behavioral repertoires. Here, we describe the evolution of walking in fruit flies by capturing high-resolution, unconstrained movement from 13 species and 15 strains of drosophilids. We find that walking can be captured in a universal behavior space, the structure of which is evolutionarily conserved. However, the occurrence of, and transitions between, specific movements have evolved rapidly, resulting in repeated convergent evolution in the temporal structure of locomotion. Moreover, a meta-analysis demonstrates that many behaviors evolve more rapidly than other traits. Thus, the architecture and physiology of locomotor circuits can both execute precise individual movements in one species and simultaneously support rapid evolutionary changes in the temporal ordering of these modular elements across clades.

In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog input, and the output is evaluated only when needed by the digital subsystem. Our architecture is therefore intended for digitally-driven systems; that is, those in which the inputs of analog dynamical blocks change only on digital clock edges. We implemented a high-speed link transceiver design using the proposed architecture on a Xilinx FPGA. This design demonstrates how our approach breaks the link between simulation rate and time resolution that is characteristic of prior approaches. The emulator is flexible, allowing for the real-time adjustment of analog dynamics, clock jitter, and various design parameters. We demonstrate that our architecture achieves 1% accuracy while running 3 orders of magnitude faster than a comparable high-performance CPU simulation.

Using digital standard cells and digital place-and-route (PnR) tools, we created a 20 GS/s, 8-bit analog-to-digital converter (ADC) for use in high-speed serial link applications with an ENOB of 5.6, a DNL of 0.96 LSB, and an INL of 2.39 LSB, which dissipated 175 mW in 0.102 mm 2 in a 16nm technology. The design is entirely described by HDL so that it can be ported to other processes with minimal effort and shared as open source.