Fast FPGA emulation of analog dynamics in digitally-driven systems

Abstract

In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog input, and the output is evaluated only when needed by the digital subsystem. Our architecture is therefore intended for digitally-driven systems; that is, those in which the inputs of analog dynamical blocks change only on digital clock edges. We implemented a high-speed link transceiver design using the proposed architecture on a Xilinx FPGA. This design demonstrates how our approach breaks the link between simulation rate and time resolution that is characteristic of prior approaches. The emulator is flexible, allowing for the real-time adjustment of analog dynamics, clock jitter, and various design parameters. We demonstrate that our architecture achieves 1% accuracy while running 3 orders of magnitude faster than a comparable high-performance CPU simulation.

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

“…There is unfortunately only one published result for the emulation performance of a fully-virtualized high-speed link: our own study from ICCAD 2018 [10]. That study, which preceded development of our emulation framework, showed that a variable timestep approach was promising for emulating high-speed links.…”

“…Emulating AMS designs on those platforms, or even on off-the-shelf FPGA boards, requires that analog blocks are replaced by synthesizable models. A wide variety of strategies for doing just that have been reported, covering applications such as power conversion [8], [9], high-speed communication [10], [11], signal conditioning [12], [13], analog-to-digital conversion [14], and analog testing [15]. Reported speedups typically ranged from two to three orders of magnitude as compared to CPU-based simulation.…”

“…1) Channel modeling: Since the system-level behavior of DragonPHY depends on both clock jitter and sub-picosecond sampling point adjustments, fine time resolution is required in emulating the design. Our strategy in achieving this resolution without significantly impacting the emulator performance leverages our past work in [10]: we have the emulator take large, but precise, timesteps, avoiding the creation of extra timesteps whose only purpose is to update analog state variables.…”

“…That study, which preceded development of our emulation framework, showed that a variable timestep approach was promising for emulating high-speed links. Since the link design studied in [10] was simpler than DragonPHY, the low-level DragonPHY emulator was about 2x slower than the ICCAD '18 result. However, the high-level DragonPHY emulator was about 8x faster.…”