20-GS/s 8-bit Analog-to-Digital Converter and 5-GHz Phase Interpolator for Open-Source Synthesizable High-Speed Link Applications

Kim, Sung-Jin; Myers, Zachary; Herbst, Steven; Lim, Byong Chan; Horowitz, Mark

doi:10.1109/lssc.2020.3037823

Cited by 5 publications

(5 citation statements)

References 8 publications

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“…We further evaluate the power consumption for static inference tasks, where the weights can be considered constant. We assumed the power required for sending and receiving an optical signal of 13.3 pJ/clock, which includes the power of an ADC, 55 a digital-to-analog converter (DAC), 56 and other components of optical interconnection such as lasers, transimpedance amplifiers, and PDs (see the Supporting Information, Section VII). In addition, the power of phase shifters should be taken into account.…”

Section: ■ Resultsmentioning

confidence: 99%

Si Microring Resonator Crossbar Array for On-Chip Inference and Training of the Optical Neural Network

Ohno¹,

Toprasertpong²,

Takagi³

et al. 2022

ACS Photonics

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Deep learning has been a powerful tool in various fields. Faced with the limits of the current electronics platform, optical neural networks (ONNs) based on Si programmable photonic integrated circuits (PICs) have attracted considerable attention as a novel deep-learning scheme with optical-domain matrix-vector multiplication (MVM). However, most of the proposed Si programmable PICs for ONNs have several drawbacks, such as low scalability, high power consumption, and lack of frameworks for training. To address these issues, we have proposed a microring resonator (MRR) crossbar array as a Si programmable PIC for an ONN. In this Article, we present a prototype of a fully integrated 4 × 4 MRR crossbar array for MVM and demonstrate a simple image classification task using this chip. Moreover, we propose on-chip backpropagation using the transpose matrix operation of the MRR crossbar array, enabling the on-chip training of the ONN. The proposed ONN scheme can establish a scalable, power-efficient deep-learning accelerator for both inference and training tasks.

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Section: ■ Resultsmentioning

confidence: 99%

Si Microring Resonator Crossbar Array for On-Chip Inference and Training of the Optical Neural Network

Ohno¹,

Toprasertpong²,

Takagi³

et al. 2022

ACS Photonics

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“…These abstractions have enabled us to successfully apply the framework to seven mixed-signal designs: an NFCpowered chip, a firmware-controlled flyback converter, a battery impedance sensor, an automotive magnetic sensor [17], an IGBT driver, a microcontroller-based automotive power management unit (PMU), and the open-source high-speed link DragonPHY [18]. Several of these applications are discussed in this paper.…”

Section: Abstractionsmentioning

confidence: 99%

“…V. APPLICATIONS Having described our emulation framework, we next discuss its application to three mixed-signal designs: an open-source high-speed link receiver called DragonPHY [18], a commercial firmware-controlled flyback converter, and a commercial NFC-powered chip. These applications cover a wide range of mixed-signal circuits and emulation use cases, demonstrating the generality of the framework.…”

Section: ) Firmware-based I/omentioning

confidence: 99%

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

Herbst

Rutsch

Ecker

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents an open-source framework for emulating mixed-signal chip designs on an FPGA. It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-and floating-point synthesizable Sys-temVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework's generality by discussing three applications: a high-speed link receiver (DragonPHY), a firmware-controlled flyback converter, and an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2-3 orders of magnitude faster than CPU simulations with real number functional models.

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“…In these solutions, generally, analog circuits are described in RTL netlists and automatically laid out in digital P&R flows. Recent works have succeeded in time-to-digital converters (TDCs) [1]- [3], phase-locked loops (PLLs) [4]- [11], low-dropout (LDO) regulators [12]- [14], and analogto-digital converters (ADCs) [15]- [24]. As the interface between the real world and digital signal processing, ADCs are widely needed in sensor and radio frequency systems.…”

Section: Introductionmentioning

confidence: 99%

“…In another work on a voltage-controlled oscillator-based (VCO-based) ADC [27], only standard cells were employed, but the circuit layout was done manually. By registering custom-designed cells to a physical library, automatic P&R flows for analog circuits were introduced [17], [19], [23], [24], [28]. Also, hybrid methods for successive-approximation-register (SAR) ADCs were proposed with SKILL language for capacitive digitalto-analog converter (CDAC) generation [29], [30].…”

Section: Introductionmentioning

confidence: 99%

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

Ojima

et al. 2021

IEEE Trans. VLSI Syst.

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We propose an all-standard-cell-based synthesizable successive-approximation-register analog-to-digital converter (SAR ADC) which is automatically placed and routed (P&R) using a commercial digital implementation tool. For higher feasibility and wider input range, a differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC) and a four-input comparator. MOSFET gate capacitance is employed for the sampling capacitor. To mitigate its capacitance variation due to input voltage and the leakage between gate and diffusion, we leave the diffusion of the standard cell floating and only use the capacitance between gate and bulk. Two prototypes have been designed in 65-nm bulk CMOS. Prototype I has been fabricated and achieves 10 MS/s, 14.3 mW, and 28.1-dB SNDR in a 6-bit architecture. The performance is improved in Prototype II by proposing a lookup table (LUT)-compensating transistor-configurable inverter-based RDAC and an OR-AND-Inverter (OAI)-based comparator and by employing a thick-oxide diffusion-floating decoupling cell for the sampling capacitor. The default LUT is created during the design phase by a script-controlled automatic simulation routine. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7-and 47.2-dB SNDRs in 6-and 8-bit versions, respectively. The power consumptions are reduced to 0.91 and 2.52 mW, respectively.

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20-GS/s 8-bit Analog-to-Digital Converter and 5-GHz Phase Interpolator for Open-Source Synthesizable High-Speed Link Applications

Cited by 5 publications

References 8 publications

Si Microring Resonator Crossbar Array for On-Chip Inference and Training of the Optical Neural Network

Si Microring Resonator Crossbar Array for On-Chip Inference and Training of the Optical Neural Network

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

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