An Optimal Analytical Solution for Processor Speed Control with Thermal Constraints

Rao, Ravishankar; Vrudhula, Sarma; Chakrabarti, Chaitali; Chang, Naehyuck

doi:10.1109/lpe.2006.4271852

Cited by 18 publications

(25 citation statements)

References 7 publications

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“…As the power density continues scaling up, the thermal-related issues are exasperated in embedded systems. Researchers have recently proposed off-line algorithms [12,13,14,15,17,22] which slow down the operating speed of the processor if needed to manage the thermal behavior of embedded systems so that the chip operates below its critical temperature. Those algorithms target deterministic applications.…”

Section: Related Workmentioning

confidence: 99%

“…As a consequence, embedded systems confront even worse thermal challenges. To solve these issues, researchers have recently proposed several thermal management techniques [12,13,14,15,17,19,22] where workloads are periodic and deterministic. In some applications, however, embedded systems run stochastic workloads [18], where novel approaches are needed to manage system thermal behavior.…”

Section: Introductionmentioning

confidence: 99%

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Hybrid of Job Sequencing and DVFS for Peak Temperature Reduction with Nondeterministic Applications

Liu

Qiu

Gao

et al. 2010

2010 10th IEEE International Conference on Computer and Information Technology

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In this paper we propose a hybrid approach, which improves system thermal behavior with nondeterministic applications based on job sequencing as well as dynamic voltage and frequency selection (DVFS). The hybrid approach consists of two steps: 1) job sequencing and 2) lowering processor's speed by using dynamic voltage and frequency selection. The first step constructs a job sequence based on the average execution time of each job; and the constructed job sequence interleaves executions of hot jobs and cool jobs. While a hot job pushes up the temperature of a chip, a cool job cools the chip down. Accordingly the job sequencing step reduces the peak temperature of a chip. The second step further improves system-wide thermal behavior by dynamic voltage and frequency selection, which slows down the execution of hot jobs by utilizing job slacks. Hot jobs are the rooted cause for deteriorating the thermal behavior of a processor, so we only slow down the execution of hot jobs and job slacks are allocated among hot jobs. Hot jobs whose execution time deviates more above their average execution time get more slack; vice versa. Experimental results show that the proposed hybrid approach improves the system thermal behavior for various nondeterministic workloads by reducing peak temperature as well as decreasing thermal variations.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hybrid of Job Sequencing and DVFS for Peak Temperature Reduction with Nondeterministic Applications

Liu

Qiu

Gao

et al. 2010

2010 10th IEEE International Conference on Computer and Information Technology

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“…While some others (e.g. [6], [10], [15], [26], [31]) intend to minimize the peak temperature or to guarantee the given maximum temperature constraints when scheduling task sets.…”

Section: Related Workmentioning

confidence: 99%

Validation of scheduling techniques to reduce peak temperature on an architectural level platform set-up

Chaturvedi

Thanarungroj

Liu

et al. 2011

2011 Proceedings of IEEE Southeastcon

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In this paper, we have proposed a novel architectural level simulation platform set-up to study the temperature characteristics of a processor system, when applying different speed scheduling schemes to execute the desired workload. Our simulation platform set-up is very practical as it combines the most practical simulation models, and uses the industrystandardized benchmark SPEC CPU2000 as the input to the platform. On this novel platform set-up we have compared two speed scheduling techniques, namely m-oscillation and a traditional optimal dynamic energy reducing speed scheduling technique, and have shown that m-oscillation can be as effective as the traditional approach in reducing the peak temperature of the system.

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“…Researchers have proposed high-level models and used them to obtain analytical results or heuristics for thermal management [3][4][5][6][7][8]. However, most of these works did not address multi-core processors and they all use very simple power/thermal models which do not capture some or all of the following important effects: (a) the variations of power-density over different chip blocks, which leads to hotspots (see [9]), (b) leakage dependence on temperature (LDT), which is significant for 65 nm and beyond (see [5,10]), and (c) the contrast in the thermal response times of the die and package.…”

Section: Introductionmentioning

confidence: 99%

Throughput of multi-core processors under thermal constraints

Rao

Vrudhula

Chakrabarti

2007

Proceedings of the 2007 International Symposium on Low Power Electronics and Design

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We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a) the maximum number of cores that can be activated, with and without throttling, (b) the speedup (multi-core over single core), and the total power consumption, both as functions of the number of active cores. These expressions involve parameters like power per core, thermal resistance of hottest die block and package, and leakage dependence on temperature. We also computed the above metrics (a) and (b) numerically by solving the detailed Hotspot circuit of an multicore processor driven by a block-level exponential temperaturedependent leakage model. When compared to these numerical results, we found that the above expressions for (a) were at most 8% underpredicted, while those for (b) were accurately predicted. The proposed analytical approach is the first of its kind to relate metrics of interest in multi-core processors to high-level design parameters. Compared to numerical approaches, it provides much faster computation time, and valuable insight for processor designers.

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An Optimal Analytical Solution for Processor Speed Control with Thermal Constraints

Cited by 18 publications

References 7 publications

Hybrid of Job Sequencing and DVFS for Peak Temperature Reduction with Nondeterministic Applications

Hybrid of Job Sequencing and DVFS for Peak Temperature Reduction with Nondeterministic Applications

Validation of scheduling techniques to reduce peak temperature on an architectural level platform set-up

Throughput of multi-core processors under thermal constraints

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