An optimal memory allocation for application-specific multiprocessor system-on-chip

Meftali, Samy; Gharsalli, Ferid; Rousseau, Frédéric; Jerraya, Ahmed

doi:10.1145/500001.500006

Cited by 52 publications

(21 citation statements)

References 16 publications

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“…Data parallelism to improve performance in a system of homogeneous multiprocessor systems is mainly the main focus of many of such research. In order to obtain optimal distributed shared memory architecture to reduce the memory and data access costs, Meftali et al [13] used an optimal integer linear programming formulation. Kandemir et al [14] used a compiler based approach to optimize energy and memory access latency on MPSoCs.…”

Section: Related Workmentioning

confidence: 99%

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Salamy¹,

Sopeju²

2014

IJCA

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As the utilization of multiprocessors system-on-chip (MPSoC) is becoming ubiquitous, demands for effective allocation and scheduling techniques are needed more than ever to harness the power of MPSoCs. An MPSoC is a system consisting of multiple heterogeneous processing cores, memory hierarchies, and communication infrastructure to effectively overcome the power and clock constraints from single core architectures. MPSoCs provide the performance demanded by embedded applications especially real-time multimedia applications. This article presents effective techniques to partitioning the processing cores and memory budget in an MPSoC among multiple embedded applications possibly entering the system at different times. The proposed framework will study the structure of each application and predict the possible reduction in schedule time if more processors and/or memory budget are assigned to this application. The objective is to fairly divide the resources such that the schedule times for the applications are minimized. Results on different embedded applications workloads and under different system resources show the effectiveness of our techniques that were able to reduce the cycle count by 10.2 % on average compared to an effective technique in the literature.

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Section: Related Workmentioning

confidence: 99%

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Salamy¹,

Sopeju²

2014

IJCA

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“…Meeuwen et al presented a technique for cost-efficient interconnect architecture exploration by time-multiplexing the data transfers over a number of shared buses assuming distributed memory systems under predetermined memory allocation [8]. Meftali et al found performance-optimal shared memory allocation considering area of communication channel and memory subsystem using integer linear programming (ILP) in a point-to-point communication architecture [9]. Lahiri et al proposed an exploration technique optimizing the component mapping to bus and the bus protocol such as DMA block transfer size and bus priority assignment for a given bus topology [5].…”

Section: Related Work and Our Contributionmentioning

confidence: 99%

Efficient exploration of bus-based system-on-chip architectures

Kim

2006

IEEE Trans. VLSI Syst.

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Abstract-Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver.

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“…Unfortunately, only limited research exists in reducing the energy cost of the memory system. [10] and [31] describe both a heuristic which does allocation, assignment, scheduling of multiple task-graphs. [24] and [58] compile a task-graph on a given heterogeneous architecture.…”

Section: Memory Optimization In Multi-threaded Applicationsmentioning

confidence: 99%

Power-efficient data management for dynamic applications

Marchal

Perez

Atienza

et al. 2006

System-on-Chip: Next Generation Electronics

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multi-processor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility also perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads running on the different processors into account, only locally optimize the bandwidth nor deal with the dynamic behavior of these applications. The contributions of this chapter are to outline the main limitations of current techniques and to introduce an approach for dealing with the dynamic multi-threaded of our application domain. The design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [53]. These systems require an enormous computational performance (40GOPS 1 ). Even though current PCs offer this performance requirement, they consume too much power (10-100W). Mobile devices should consume at least two or three orders of magnitude less power [30]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. The era of platform-based designA platform is a fixed micro-architecture together with a programming environment that minimizes mask-making costs and is flexible enough to work for a set of applications [4]. The production volumes can then remain high over an extended chip lifetime.Given the strong energy constraints, we must choose the flavor of these platforms. Since power is cubic to the processing frequency, parallelism is an effective to reduce power and energy consumption. Then, multiple simple processors are preferred to one complex speculative and out-of-order processor. In the right application domain, we can get better performance and spend less energy. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a Digital Signal Processor (DSP). The RISC is more energy-efficient for the input/output processing and simple control-dominated 1 Giga Operations Per Second

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An optimal memory allocation for application-specific multiprocessor system-on-chip

Cited by 52 publications

References 16 publications

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Efficient exploration of bus-based system-on-chip architectures

Power-efficient data management for dynamic applications

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