An Optimized Architecture for Binary Huff Curves With Improved Security

Abstract

In order to compute the elliptic curve point addition and doubling, the unified point addition law provides better protection against side channel attacks. One of the elliptic curve models, providing the unified point addition, is Binary Huff Curves (BHC). Recently, a new unified method for BHC with improved security against side channel attacks, has been proposed. Therefore, an optimized hardware architecture in terms of higher clock frequency and throughput for the new unified point addition method is required. Consequently, this article has three major contributions: The first contribution is to modify the unified addition law from hardware implementation point of view, resulting 31% decrease in memory requirements. The second contribution is the analysis of memory optimized unified law in the context of pipelining. In this regard, this article proposes an instruction scheduling policy for a 2-stage pipelined architecture which provides 36% reduction in the number of required clock cycles, 14.3% improvement in clock frequency, 53.2% decrease in computation time and 54.5% improvement in throughput/area. Finally, the third contribution is to propose a 4-stage pipelined architecture. The proposed 4-stage pipelined architecture provides an additional 19% improvement in clock frequency and 10% increase in throughput, as compared to the 2-stage pipelined architecture.

DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication

“…The BHC model requires larger memory for keeping initial, intermediate, and final results, while on the other hand, the Weierstrass model needs lower memory size. With 4-stage pipelining in [15], the obtained operating frequency is 371 MHz, higher than our nonpipelined accelerator, which obtained 350 MHz. Rather than the operating frequency, our hardware accelerator outperforms in latency, throughput, and FoM results, as shown in Table 2.…”

“…The design of [14] describes a hardware accelerator for FPGA devices, where a Weierstrass ECC model over a GF (P ) field, with P = 256, has been implemented. The BHC curve is considered for hardware acceleration in designs of [15], [16]. These hardware accelerators use 2-stage and 4-stage pipelining to shorten the circuit's critical path, which also helps improve the circuit frequency.…”

“…This aspect is particularly critical for a wide range of constrained applications, including radio-frequency identification networks (RFID), wireless sensor networks (WSNs), and Internet of Things (IoT) [33]- [37]. Rather than that, the designs of [15], [16], [38]- [40] utilize different optimization approaches, (i) incorporation of various modular operations in the datapath of the processor, (ii) different stage pipelining either in the accelerators datapath or in the modular multipliers, (iii) instruction-level parallelism, etc., for optimizing performance or throughput of the accelerator. However, these optimization approaches have introduced hardware resource overheads, rendering them unsuitable for applications like RFID and WSNs.…”

“…Despite the Weierstrass ECC model implementations, the design of [15] focuses on a specialized BHC model of ECC for hardware acceleration. The reference architecture has described pipelined architectures, but we have considered the most optimized one (i.e., 4-stage) for our comparison.…”

“…Rather than the operating frequency, our hardware accelerator outperforms in latency, throughput, and FoM results, as shown in Table 2. In addition, our non-pipelined hardware accelerator consumes less power than the 4-stage pipelined accelerator of [15]. This is due to using different ECC models: Weierstrass in our implementation while BHC in the reference design.…”