An Optimized Compression Strategy for Compressor-Based Approximate Multiplier

Wang, Manzhen; Luo, Yuanyong; An, Mengyu; Qiu, Yuou; Zheng, Muhan; Wang, Zhongfeng; Pan, Hongbing

doi:10.1109/iscas45731.2020.9181066

Cited by 8 publications

(4 citation statements)

References 13 publications

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“…Partial product (PP) approximation: a wide class of works targeting imprecise multipliers have mostly applied approximation on: 1) PP generation by simplification of truth table in e.g., 2×2 and 4×4 multipliers and use them in a modular design [22]. 2) Reduction/accumulation of PP rows into two, using 3:2 and 4:2 imprecise compressors [23,24,25,26,14,27,28] in Dadda-or array-based multipliers. or 3) Adding the reduced PP rows by e.g., splitting the carry propagation path [7,29].…”

Section: Related Workmentioning

confidence: 99%

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

Ebrahimi

Zaid

Wijtvliet

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The rapid updates in error-resilient applications along with their quest for high throughput has motivated designing fast approximate functional units for Field-Programmable Gate Arrays (FPGAs). Studies have proposed various imprecise functional techniques, albeit posed with three shortcomings: first, most existing inexact multipliers and dividers are specialized for Application-Specific Integrated Circuit (ASIC) platforms. Therefore, due to the architectural differences of underlying building blocks in FPGA and ASIC, ASIC-customized designs have not yielded comparable improvements when directly synthesized and ported to FPGAs. Second, state-of-the-art (SoA) approximate units are substituted, mostly in a single kernel of a multi-kernel application. Moreover, the end-to-end assessment is adopted on the Quality of Results (QoR), but not on the overall gained performance. Finally, existing imprecise components are not designed to support a pipelined approach, which could boost the operating frequency/throughput of, e.g., divisionincluded applications. In this paper, we propose RAPID, the first pipelined approximate multiplier and divider architectures, customized for FPGAs. The proposed units efficiently utilize 6-input Look-up Tables (6-LUTs) and fast carry chains to implement Mitchell's approximate algorithms. Our novel error-refinement scheme not only has negligible overhead over the baseline Mitchell's approach, but also boosts its accuracy to 99.4% for arbitrary size of multiplication and division.Experimental results obtained with Xilinx Vivado demonstrate the efficiency of the proposed pipelined and non-pipelined RAPID multipliers and dividers over accurate counterparts. In particular, 4-stage pipelined architecture of 32-bit RAPID multiplier (divider) enables 3.3× (5.1×) higher throughput, 2.3× (6.8×) higher throughput/Watt, and 52% (31%) savings of LUTs, over their 4-stage pipelined, accurate IP counterparts. Moreover, the end-to-end evaluations of non-pipelined RAPID, deployed in three multi-kernel applications in the domains of bio-signal processing, image processing, and moving object tracking for Unmanned Air Vehicles (UAV) indicate up to 35%, 33%, and 45% improvements in area, latency, and Area-Delay-Product (ADP), respectively, over accurate kernels, with negligible loss in QoR. To springboard future research in reconfigurable and approximate computing communities, our implementations will be available and open-sourced at https://cfaed.tu-dresden.de/pd-downloads.

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Section: Related Workmentioning

confidence: 99%

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

Ebrahimi

Zaid

Wijtvliet

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Due to the difference in the significance of groups, each group can be assigned with different levels of approximation [47,[49][50][51][52][53][54]. While the first group is always allocated with exact compressors, the second group can be allocated with either approximate compressors using equally weighted outputs [49,50] or high-order approximate compressors with error recovery [51,52]. For the last group, one straightforward approach is to completely ignore it [47,53].…”

Section: Allocation Of Approximate Compressors In the Compressormentioning

confidence: 99%

“…Various new techniques have been introduced at different stages of a binary multiplication following the conventional data flow [24,36,[43][44][45][46][47][47][48][49][50][51][52][53][54][55][56].…”

Section: Introductionmentioning

confidence: 99%

A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits

Wu¹,

Chen²,

Xiao³

et al. 2023

Preprint

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Given the stringent requirements of energy efficiency for Internet-of-Things edge devices, approximate multipliers have recently received growing attention, especially in error-resilient applications. The computation error and energy efficiency largely depend on how and where the approximation is introduced into a design. Thus, this article aims to provide a comprehensive review of the approximation techniques in multiplier designs ranging from algorithms and architectures to circuits. We have implemented representative approximate multiplier designs in each category to understand the impact of the design techniques on accuracy and efficiency. The designs can then be effectively deployed in high level applications, such as machine learning, to gain energy efficiency at the cost of slight accuracy loss.CCS Concepts: • General and reference → Surveys and overviews; • Hardware → Arithmetic and datapath circuits; System-level fault tolerance.

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“…The inexact multiplier is realized using these proposed compressors with less error difference, and vital improvements are gained in terms of speed, area, and power. A universal strategic compressor‐based multiplier is described by Wang et al 18 In this work, shortcomings of previous approximate compressor‐based multipliers are defeated by the proposed method with acceptable error, and the overhead area is reduced. Dharmaraj et al 19 recommended the low‐power approximate adders and multipliers, which are accepted in digital signal processing applications.…”

Section: Introductionmentioning

confidence: 99%

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

Odugu

C²,

2021

Circuit Theory & Apps

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The very large‐scale integration (VLSI) design‐based architectures of 2‐D filters must have low power consumption and high speed rather than accuracy for image processing applications. The inexact computations reduce the delay, area, and power in arithmetic architectures, and utilizing this advantage an approximation can be introduced in 2‐D digital filters. In this work, circular symmetry is adopted to optimize the 2‐D finite impulse response (FIR) filter architecture, and it is implemented using imprecise multipliers and approximate compressors with acceptable accuracy. The exact 4:2 compressor is modified into an approximate 4:2 compressor by ignoring few inputs. Hence, hardware requirement and delay parameters are improved. The proposed compressor is designed by mixed logic rather than complete complementary metal‐oxide semiconductor (CMOS) logic. The dual value logic (DVL), transmission gate logic (TGL), and CMOS mixed logic gates are used to decrease the number of transistors in the circuits. The proposed compressors are used in the approximate Dadda multiplier (ADM). The ADMs are utilized to implement the 2‐D FIR filter architecture. The designed filter is coded in Verilog and implemented using field programmable gate array (FPGA). The hardware utilization is analyzed and compared with exact 2‐D FIR filters. Next, the proposed architecture is synthesized using Cadence genus tools, and physical design is carried out by Cadence Innovus tools in 45‐nm CMOS technology. The final physical design layout‐area, power, and delay reports are correlated with existing state‐of‐artworks. It is found that the proposed 2‐D FIR filter outperforms the existing works.

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An Optimized Compression Strategy for Compressor-Based Approximate Multiplier

Cited by 8 publications

References 13 publications

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

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