An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect

Abstract

In this paper, we report an ultra-low power successive-approximation-register (SAR) analog-to digital converter (ADC) by using a DAC timing strategy with considering overshoot effect to increase the sampling rate. This ADC is simulated for power supplies voltage of 0.6 V and 1.2 V in a 130-nm CMOS technology. The results indicate an ENOB greater than 9.3 bits for its full sampling-rate range (4 to 32 MS/s) with an FOM=5.3 to 9.3 fJ/conv-step.

A Low Phase Noise, Low Power and Wide Tuning Range VCO with Filtering Technique in ISM Band

“…VCO is one of the newest comparator types [2]- [4]. VCO-based comparator and quantizer are one of the most important sections of successive approximation ADC and delta-sigma, respectively [5]- [10]. The similarity between electrical oscillators and optical oscillators including lasers [11]- [20] and vertical-cavity surface-emitting lasers (VCSELs) [21]- [33] allows the processes used in optical spectroscopy to be applied.…”

De-Noising of ECG Signals by Design of an Optimized Wavelet

“…When the voltage of the ECG waveform is at least larger than 75% of the peak value of the ECG in the comparator stage (digital-comparator) [3]- [5] of the peak detector, it allows oscillation generator to be fed into speaker for beeping. Digitizing ECG signals carry out using successive approximation ADC control system [6] [7] or delta-sigma analog to digital converter (decimation filter) [8]- [12]. In order to generate an error signal, a subtractor configures to subtract the filtered ECG signal that is generated by the adder [13] from the ECG signal input to the inputter.…”