An Optimized Method for Nonlinear Function Approximation Based on Multiplierless Piecewise Linear Approximation

Yu, Hongjiang; Guo-shun, Yuan; Kong, Dewei; Lei, Lei; He, Yufeng

doi:10.3390/app122010616

Cited by 2 publications

(4 citation statements)

References 29 publications

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“…Then Lyu et al [14] built PLAC without Multiplier. This architecture is optimized by Yu et al [30] to find the minimum number of segments and reduce the maximum absolute error (MAE). All those authors worked on the range [0,1) for design their circuits.…”

Section: Piecewise Approximations Approachmentioning

confidence: 99%

Low-Power and Low-Latency Hardware Implementation of Approximate Hyperbolic and Exponential Functions for Embedded System Applications

Dalloo,

Humaidi,

Mhdawi

et al. 2024

IEEE Access

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The hyperbolic and exponential functions are widely used in various applications in engineering fields such as machine learning, IoT, signal processing, etc. To fulfill the needs of future applications effectively, this paper proposes a low-latency, low-power, acceptable accuracy and low-cost architecture for computing the approximate exponential function e ±x and, the hyperbolic functions sinh(x) and cosh(x) using a table-driven algorithm, named by Approximate Composited-Stair Function (ApproxCSF). By adopting a FPGA, the proposed design is realized and demonstrates significant improvements in terms of latency, hardware cost, power consumption, and MSE by 91%, 96%, 74%, and 99%, respectively, compared to the state-of-the-art. Xilinx Virtex-5/7 FPGAs have been employed throughout the functional verification and prototype processes. Compared to related works, it shows that the proposed architectures are much better for low-cost, and low-latency computations of exponential, hyperbolic functions than CORDIC, stochastic computation, and the Look-Up Table approaches. The source code is publicly available online.

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Section: Piecewise Approximations Approachmentioning

confidence: 99%

Low-Power and Low-Latency Hardware Implementation of Approximate Hyperbolic and Exponential Functions for Embedded System Applications

Dalloo,

Humaidi,

Mhdawi

et al. 2024

IEEE Access

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show abstract

“…Among them is the scheme of piecewise linear approximation, which has good hardware performance that is realized by shift-and-add operations. In [13], the piecewise linear approximation scheme with the best performance is proposed.…”

Section: Introductionmentioning

confidence: 99%

“…In the research, we adopt the method of hardware implementation described in [13] and focus solely on scenarios where the activation function is realized via a single shift-and-add operation, without differentiating the types of activation functions. In practical applications, it is sufficient to simply modify the hardware structure according to [13] for different activation functions without any modification at the instruction level. Furthermore, this method can also be extended to optimize other group data operations.…”

Section: Introductionmentioning

confidence: 99%

“…Other research work on RISC-V-based dedicated processors is basically optimized on hardware implementation, whereas our work not only optimizes at the hardware level (alternate reading and writing, length adaptation), but also adopts the current state-of-theart piecewise linear approximation method in [13] proposed by us, which is optimized in principle. Moreover, we also conducted optimization research at the instruction level.…”

Section: Introductionmentioning

confidence: 99%

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An Optimized Implementation of Activation Instruction Based on RISC-V

Guo-shun

Kong

et al. 2023

Electronics

Self Cite

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Activation is an important component of the neural network, and the standard instructions of RISC-V are difficult to use to effectively handle the activation of the array. In this paper, we propose an optimized implementation of activation instruction based on RISC-V. Based on the opensource RISC-V processor Hummingbird E203, we designed a special instruction for the implementation of activation functions. A single instruction is chosen to implement the entire activation operation, including data loading, data arithmetic and data write-back. At the hardware level, we designed a method of alternate reading and writing that only needs a small hardware storage unit to meet the requirements of the activation operation for long arrays without affecting the activation efficiency. In addition, we added the length of the array as a new parameter to instruct our designed hardware to adapt to any length of arrays. Finally, the scheduling method of some instructions in the activation process was optimized in accordance with the law of instructions, which improves the execution efficiency of instructions. Considering an activation process with an array length of 15, our design demonstrates a 4.89-fold increase in speed compared to RISC-V standard instructions while consuming only 7.78% of the energy.

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An Optimized Method for Nonlinear Function Approximation Based on Multiplierless Piecewise Linear Approximation

Cited by 2 publications

References 29 publications

Low-Power and Low-Latency Hardware Implementation of Approximate Hyperbolic and Exponential Functions for Embedded System Applications

Low-Power and Low-Latency Hardware Implementation of Approximate Hyperbolic and Exponential Functions for Embedded System Applications

An Optimized Implementation of Activation Instruction Based on RISC-V

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