An Optimum Architecture for Continuous-Flow Parallel Bit Reversal

Abstract

With the aim of minimizing memory and latency, this letter presents a novel bit-reversal architecture for continuous-flow parallel pipelined FFT processors. It harnesses the theory that any permutation can be decomposed to a series of elementary bit-exchanges. The main contribution of this letter are twofold.First, it achieves continuous-flow bit reversal in parallel with the minimum memory and minimum latency.Second, the architecture, composed of memory and 2-to-1 multiplexers, are simple and regular for general power-of-2 parallelism. Furthermore, it supports different common radices, including radix-2,radix-4, and radix-8. Index Termsfast Fourier transform (FFT), continuous-flow parallel architecture, Bit-reversal architecture.

Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal

“…The proposed circuit includes a pp permutation and a sp one. It requires 8 delays, 8 multiplexers and has a latency of 1 clock cycle, which matches equations (9), (10) and (11).…”

“…previous approaches based on delays use ss-pp-ss-pp [10] or ss-sp [11]. By contrast, the proposed approach uses memories and ss-pp for N > P 2 , and pp-sp for N ≤ P 2 .…”

“…The permutation blocks in the figure have several stages with ss, or pp or sp permutations. The first approach consists of the composition of the permutations ss-pp-ss [7], the second approach is ppss-pp [5]- [9], the third approach is ss-sp [11] and the forth one is ss-pp-ss-pp [10].…”

“…Previous ss-pp-ss and pp-ss-pp approaches use a set of buffers for the pp permutation and a memory for the ss permutation [5]- [9]. Conversely, previous ss-sp and ss-pp-sspp approaches use delays for ss and sp permutations [10], [11].…”

“…In the last years, researchers have provided efficient circuits to calculate the bit reversal of a continuous data flow arriving in series [4] or in parallel [5]- [11]. The calculation of parallel bit reversal has become popular due to the increasing number of high throughput FFT hardware architectures that have been proposed in the last years.…”