An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

Jang, Sungchun; Kim, Sung Woo; Chu, Sang-Hyeok; Jeong, Gyu-Seob; Kim, Yoonsoo; Jeong, Deog‐Kyoon

doi:10.1109/tcsii.2015.2435691

Cited by 41 publications

(9 citation statements)

References 8 publications

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“…They performed the jitter tolerance tests to show the effective tracking of low-frequency and filtering of high-frequency simultaneously. Jang et al [24] proposed the ADPLL with phase frequency detector tracking of optimal loop gain for the low jitter. The formulation of autocorrelation function denoted the operating state of ADPLL on either non-linear or random noise regime.…”

Section: Related Workmentioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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High-clock skew variations and degradation of driving ability of buffers lead to an additional power dissipation in Clock Distribution Network (CDN) that increases the dimensionality of buffers and coordination among flip-flops. The manual threshold level to predict the Region of Interest (ROI) is not applicable in clustering process due to the complexities of excessive wire length and critical delay. This paper proposes the Distance and Load Weight Updated Clustering (DLWUC) to determine the suitable position of logical components. Initially, the DLWUC utilizes the Hybrid Weighted Distance (HWD) to estimate the distance and construct the distance matrix. The weight value extracted from the sorted distance matrix facilitates the projection of buffers. The updated weight value serves as the base for clustering with labeled outputs. The placement of buffer at the suitable place from load weight updated clustering provides the necessary trade-off between clock provision and load balance. The DLWUC discussed in this paper reduces the size of buffers, skew, power and latency compared to the existing topologies.

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Section: Related Workmentioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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“…The digital implementation of the loop filter enables AD-PLLs to benefit from technology scaling. Moreover, powerful calibration and control loops could be implemented with ADPLLs to correct analog non-idealities and to optimize loop dynamics [3], [4]. The block diagram of a conventional Integer BBPLL is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…The BBPLL output phase jitter is composed of a random noise component introduced by the analog circuits and a quantization noise component introduced by the BBPD [4]. If the random noise component is larger than the quantization noise component, the BBPLL operates in a linear regime and the BBPD maintains a linear characteristic calculated by (1), where σ ∆t is the standard deviation of the normal distribution of the time error input to the BBPD.…”

Section: Introductionmentioning

confidence: 99%

“…Consequently, optimizing the BBPLL bandwidth is not straight forward because the BBPD characteristic depends on random noise to quantization noise ratio which is a function of the bandwidth. Therefore, in [4] a loop-gain control loop running in background to automatically adapt the DLF proportional gain (β) to obtain the optimum BBPLL bandwidth is proposed. This optimum BBPLL bandwidth occurs at the boundary between the linear and non-linear operation regimes and is characterized by BBPD output with zero autocorrelation as illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

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A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs

2023

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This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC linear dynamic range equals the range of the input time error. Consequently, PLL in-band phase noise is reduced due to reduction of the Power Spectral Density (PSD) of the TDC quantization noise. Moreover, the linearity of the TDC transfer function across the range of the input time error is guaranteed. On contrary, the counterpart resolution control loop based on Lloyd-Max algorithm does not guarantee the linearity of the TDC transfer function across the range of the input time error. Furthermore, the proposed resolution control loop achieves TDC quantization noise with a lower variance compared to that achieved by the counterpart resolution control loop when applied with a TDC with more than 3 bits. Finally, the hardware implementation of the proposed resolution control loop is more area and power efficient compared to the implementation of the counterpart resolution control loop.

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“…Fig6represents Block schematic diagram and circuit connection of analog phase lock loop circuit. Figure7represents complete hardware of PLL circuit [8]. This whole circuit is used to synchronize line frequency sine wave signal with PWM signal.…”

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confidence: 99%

Line Synchronised Control Pulses for Three Phase Induction Motor AC-AC Drive Using Analog Phase Lock Loop Technique

Deshmukh¹,

Barhate²,

Tutakne³

2020

helix

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Technique used in this research is to obtain high operating efficiency of three phase induction motor (IM). To achieve this emphasis is given on minimizing the core losses by controlling the magnetizing current of three phase induction motor so that total power loss gets reduced and thereby efficiency of IM gets improved. Improvement in power factor of IM causes reduction in magnetizing current. Novel topology used in this work also aimed at controlling the speed and improvement of power factor separately. To improve the performance and to obtain the expected results of induction motor at any change in operating frequency ,work is focused on obtaining line synchronised extinction angle (β) and Pulse Width Modulation(PWM) control pulses. Both these controls are line synchronized using analog phase lock loop(PLL) technique so that switching frequency of PWM pulses remains synchronized with the supply frequency for any small change in input supply frequency, so that separate smooth control over wide range of speed and improvement in power factor both are achieved. Switching off supply at extinction angle β gives improvement in power factor and variation in duty ratio of PWM pulses controls the speed of three phase induction motor. Hardware and simulation results are obtained by using only four switches , which simplifies the circuit and makes it cost effective. The hardware model for line synchronised control pulses using analog PLL technique is shown. PLL has many applications.

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An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

Cited by 41 publications

References 8 publications

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs

Line Synchronised Control Pulses for Three Phase Induction Motor AC-AC Drive Using Analog Phase Lock Loop Technique

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