An out-of-order three-way superscalar multimedia floating-point unit

A New High Radix-2<SUP>r</SUP> (<I>r</I> ≥ 8) Multibit Recoding Algorithm for Large Operand Size (<I>N</I> ≥ 32) Multipliers

“…Likewise, using theorem (2), each 16+1 bit slice is split into 8+1, 5+1, 2+1, and 1+1 overlapping slices using Seidel radix-2 8 …”

“…Based on the total number of adders (Add T ), the critical path of the multiplier in terms of logic levels is: 8 . Table II provides the area occupation and delay for each recoding algorithm.…”

“…We used for comparison a two's complement 64×64 bit parallel multiplier. The implementation results are grouped in Table III. Although 8 ) on the total performance is important (Table III). Besides, it is the most area consumer despite the fact that it employs the lowest number of adders (N/4-1).…”

“…A hybrid radix-4/-8 is proposed in [3] for low-power multimedia applications. To increase the speed of the multiplier, most ancient processors employed radix-8, such as: Fchip [4], IBM S/390 [5], Alpha RISC [6], IA-32 [7] and AMDK7 [8]. While radix-16 is used only in the most recent Intel processors: 64 and IA-32 [9], and Itanium-Poulson [10].…”

“…Section I outlines the main requirement specifications for a generalized radix-2 r multiplication. Section II introduces the new recursive multibit recoding multiplication algorithm, illustrated by two high-radix (2 8 and 2 16 ) recoding examples in Section III. Section IV introduces some preliminary steps toward an optimal partitioning of the multiplier architecture, while the optimal partitioning is presented in Section V. Section VI compares and discusses the implementation results.…”