An Outlook on Design Technologies for Future Integrated Systems

Micheli, Giovanni De

doi:10.1109/tcad.2009.2021008

Cited by 30 publications

(14 citation statements)

References 131 publications

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“…These are, as a minimum, scalar 32-bit central processing units (CPUs), digital signal processors (DSPs) augmented either by data-level parallel (DLP) standalone coprocessors [1], instruction set architecture (ISA) extensions or combinations thereof [2], connected via numerous, high bandwidth, point-to-point buses and more recently, packet-switched networks [3]. These units are supplied by many local memory blocks under the control of Direct Memory Access (DMA) engines.…”

Section: Introductionmentioning

confidence: 99%

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Chouliaras

Stevens

Dwyer

2016

Microprocessors and Microsystems

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performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and~13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores VThreads demonstrates a post-route (statistical) power reduction between 65% to 57% at an area increase of 1.2%-10% for 1-8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support.

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Section: Introductionmentioning

confidence: 99%

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Chouliaras

Stevens

Dwyer

2016

Microprocessors and Microsystems

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“…Fumihito [2] analyse the balance of the adhesive forces between the objects, and proposed reduction method of adhesive force. J. Norberto Pires [3], Choon-Young Lee [4], propose a novel module and a new algorithm which are applied on mobile robot to avoid obstacles using three ultrasonic sensors with different beam widths. Object detection systems work in real-time is addressed by W. Zhang [5] by uses images processing at various resolutions.…”

Section: Introductionmentioning

confidence: 99%

Multiple Sensor Integrated Robotic End-effectors for Assembly

Sahu

Biswal

Mukherjee

et al. 2014

Procedia Technology

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In industrial environment product assembly constitutes a major part in manufacturing. Introduction of automation in manufacturing activities has positively influenced the business in many counts. With the advent of new technologies manufacturing houses are willing to adopt new technologies and strategies to make their products more reliable and competitive. The present work deals with the development of a multiple sensor integrated robot end-effector which can be gainfully used for product assembly in industries. The sensors prescribed for the purpose help the assembly robot in identifying the correct part, navigation the robot arm and inspecting the assembly for its correctness. Experiments on these aspects have been conducted successfully and the relevant results are presented to explain the effectiveness and usefulness of the sensor integrated endeffector.

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“…Furthermore, the rapid increase in the capability and complexity of applications increases the density and complexity of on-chip interconnects. Two solutions to alleviate the problem of interconnects are NoCs [1] and 3D integrated circuits (3D ICs) [2] [3].…”

Section: Introductionmentioning

confidence: 99%

“…By combining these two techniques, we take advantage of their different benefits [2]. In a 3D IC, various layers of components are stacked vertically on each other; communication among these layers is through vertical interconnects.…”

Section: Introductionmentioning

confidence: 99%

Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip

Hamedani

Jerger

Hessabi

et al. 2013

International Journal of Adaptive, Resilient and Autonomic Systems

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This paper proposes three ILP-based static thermal-aware mapping algorithms for 3D Networks-on-Chip (NoC). With these three mapping algorithms, the authors explore the thermal constraints and their effects on temperature and performance. Through complexity analysis, the authors show that the first algorithm, an optimal one, is not suitable for 3D NoCs. Therefore, the authors develop two approximation algorithms and analyze their algorithmic complexities to show their proficiency. According to simulation results, mapping algorithms that employ direct thermal calculation to minimize the temperature reduce the peak temperature by up to 24% and 22%, for the benchmarks that have the highest communication rate and largest number of tasks, respectively. This peak temperature reduction comes at the price of a higher power-delay product. The authors’ exploration shows that considering power balancing early in the mapping algorithm does not affect chip temperature. Moreover, the authors show that considering explicit performance constraints in the thermal mapping has no major effect on performance.

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An Outlook on Design Technologies for Future Integrated Systems

Cited by 30 publications

References 131 publications

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Multiple Sensor Integrated Robotic End-effectors for Assembly

Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip

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