An ovenview of SBU (Sequential Build-Up)/Microvia technologies?

Ho, Irving T.

doi:10.1109/isapm.1997.581245

Cited by 6 publications

(1 citation statement)

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“…The evolution of characteristic dimensions over time for build-up layers and cores is shown in Table 2. An overview of SBU technologies has been published [17]. In addition, for the following illustrative ASIC design case, the package pins can be classified in six groups: power, ground, serial embedded differential, source-synchronous single-ended, source-synchronous differential (which may be edge-or broadside-coupled, parallel or offset), and common clock single-ended ( Figure 4).…”

Section: Figurementioning

confidence: 99%

The evolution of build-up package technology and its design challenges

Blackshear

Cases²,

Klink

et al. 2005

IBM J. Res. & Dev.

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This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988. It reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications.

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Section: Figurementioning

confidence: 99%