An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection

Chen, Xiaoding; Hsiao, Michael S.

doi:10.1109/tvlsi.2007.893657

Cited by 12 publications

(3 citation statements)

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“…In the scan architectures [4,7], which can reduce both shift power and capture power, shift power is reduced by allowing only a part of scan chains to receive test data. Capture power is reduced, either by using a part of scan flip-flops to receive the response [4,7], or by capturing response in different cycles [4].…”

Section: Introductionmentioning

confidence: 99%

“…Capture power is reduced, either by using a part of scan flip-flops to receive the response [4,7], or by capturing response in different cycles [4].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, we try to use DFT based method to reduce power with little area overhead. In the previous DFT based methods [4,7], which can reduce both shift and capture power, they use the correlation of patterns to partition the scan chains. These methods are test set dependent and the results depend on the character of test vectors.…”

Section: Introductionmentioning

confidence: 99%

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A Low Power Architecture based on Unidirectional Cut

Chen

Xiang

2009

ECS Trans.

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Test power of a circuit mainly consists of capture power and shift power. In this paper, a new scan architecture is proposed to reduce both of them. In the architecture, a new graph algorithm is proposed to partition the scan flip-flops into two parts and then the ones with common successors in each part are grouped as a chain. By partitioning the scan flip-flops into two parts, the process of capture is cut into two sequential steps. This technique can effectively reduce the capture power. Using the clock disabling scheme, we can make sure that, only one or a small portion of scan chains are active during the shifting phase. Therefore, the peak power and average power are reduced. This architecture can effectively reduce the test time too. Experimental result shows that average power and peak power reduction are very significant, compared with the ordinary full-scan architecture.

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Section: Introductionmentioning

confidence: 99%

“…Capture power is reduced, either by using a part of scan flip-flops to receive the response [4,7], or by capturing response in different cycles [4].…”

Section: Introductionmentioning

confidence: 99%