An overview of advanced FPGA architectures for optimized hardware realization of computation intensive algorithms

Qasim, Syed Manzoor; Abbasi, Shuja A.; Almashary, B.

doi:10.1109/mspct.2009.5164235

Cited by 9 publications

(3 citation statements)

References 8 publications

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“…CA units of CU are based on commonly available integrated circuits (CMOS), therefore they are much larger than intended for a real application, which most likely would combine field programmable gate arrays (FPGA) with printed circuit boards (PCB) [64]. On the other hand, due to high cost of LC elements, SP is much smaller than intended.…”

Section: Implementation Of Pfss In Square Gridmentioning

confidence: 99%

Dynamic shading of a building envelope based on rotating polarized film system controlled by one-dimensional cellular automata in regular tessellations (triangular, square and hexagonal)

Zawidzki

2015

Advanced Engineering Informatics

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Section: Implementation Of Pfss In Square Gridmentioning

confidence: 99%

Dynamic shading of a building envelope based on rotating polarized film system controlled by one-dimensional cellular automata in regular tessellations (triangular, square and hexagonal)

Zawidzki

2015

Advanced Engineering Informatics

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“…arama sorusuna sonuç olarak ana kelimeye ait alternatif "kumpir nedir", "kumpir tarifi", mekân adresleri gibi sonuçlar üreten algoritmalardır. [6][7][8]. Uygulama programları F-CCM'lere uyarlanırken, programın yüksek işlemci gücü gerektiren bölümleri özel olarak tasarlanmış donanım modülü kullanılarak FPGA çipleri üzerinde çalıştırılır ve bu sayede programın daha hızlı çalışması sağlanır [9].…”

Section: Gi̇ri̇ş (Introduction)unclassified

Yüzde Tabanli Stri̇ng Eşleme Problemi̇ İçi̇n Yeni̇ Bi̇r Donanim Modülü Tasarimi

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2016

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Bir verinin bir dizgi içerisinde veya bir gen yapısının bir DNA gen dizilimi içerisinde arama işleminin gerçekleştirilmesi için çeşitli algoritmalar kullanılmaktadır. Kullanılan bu algoritmalardan bazıları bize mutlak eşleşme olmadığı durumlarda olumsuz dönüt vermekte, bazıları ise "bunu mu arıyorsunuz" diye alternatifler sunmaktadır. Her iki algoritma da genel amaçlı PC'lerde saniyeler süren işlemler sonucunda bize dönüt verebilmektedir. Bu çalışmada bize hem mutlak eşleşmeyi hem de hedef dizgi içinde yüzdelik eşleşme oranlarının gerçekleştiği konumu veren FPGA çiplerine yönelik yüksek performanslı bir donanım modülü tasarlanmıştır. Geliştirilen modülün veri işleme hızı farklı PC'lerle karşılaştırılmış ve 2300 kata kadar daha hızlı arama gerçekleştirdiği karşılaştırma sonuçlarından elde edilen veriler ile doğrulanmıştır.

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“…Today, FPGAs are increasingly used to build complex integrated video processing applications. FPGAs offer cheap and fast programmable silicon among the most advanced fabrication processes [11]. Furthermore, FPGA technology enables to implement massively parallel architectures due to the huge number of programmable logic fabrics available on the chip [4].…”

Section: Introductionmentioning

confidence: 99%

A generic pixel distribution architecture for parallel video processing

Ali¹,

Atitallah²,

Hanafi³

et al. 2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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I/O data distribution for neighbourhood operations processed in parallel computing dominates the multimedia video processing domain. Hardware designers are confronted with the challenge of architecture obsolescence due to the lack of flexibility to adapt the I/O system while upgrading the parallelism level. The usage of reconfigurable computing solves the problem partially with the capability of hardware partitioning according to the application requirements. Taking this aspect into consideration, we propose a generic I/O data distribution model dedicated to parallel video processing. Several parameters can be configured according to the required size of macro-block with the possibility to control the sliding step in both horizontal and vertical directions. The generated model is used as a part of the parallel architecture processing multimedia applications. We implemented our architecture on the Xilinx Zynq ZC706 FPGA evaluation board for two applications: the video downscaler (1:16) and the convolution filter. The efficiency of our system for distributing pixels among parallel IPs is demonstrated through several experiments. The experimental results show the increase in the design productivity using the automatic code generation, the low hardware cost of our solution and how flexible is the model to be configured for different distribution scenarios.

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An overview of advanced FPGA architectures for optimized hardware realization of computation intensive algorithms

Cited by 9 publications

References 8 publications

Dynamic shading of a building envelope based on rotating polarized film system controlled by one-dimensional cellular automata in regular tessellations (triangular, square and hexagonal)

Dynamic shading of a building envelope based on rotating polarized film system controlled by one-dimensional cellular automata in regular tessellations (triangular, square and hexagonal)

Yüzde Tabanli Stri̇ng Eşleme Problemi̇ İçi̇n Yeni̇ Bi̇r Donanim Modülü Tasarimi

A generic pixel distribution architecture for parallel video processing

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