An Overview of Failure Mechanisms in Embedded Flash Memories

Abstract

Non-volatile Flash memories are becoming more and more popular for System-on-Chip design (SoC). Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. Studies of realistic failure mechanisms and their associated fault models are the first mandatory step before providing efficient and practical new test methods. In this paper, we present an analysis made on actual failures occurring in 2T FLOTOX cells of 0.15µm NOR-based embedded flash structure.

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

“…The first step of our study on the 2T-FLOTOX structures has been presented in [1], where we have proposed a qualitative analysis of actual defects occurring in the memory array. Now, we have to perform electrical simulations in order to validate the possible faulty behaviors of the eFlash in presence of these defects.…”

“…In this context we have performed a qualitative analysis of defects appearing in 2T-FLOTOX core-cell as well as in the eFlash array [1]. These defects were reported from experiments on ATMEL 0.15µm eFlash technology.…”

“…So, among all possible defects [1] that may affect the eFlash array, we here focus only on the resistive shorts metal/poly which corresponds to possible resistive defects between WL and BL nodes. We have selected these defects since they impact the entire eFlash array compared to the others presented in [1]. This resistive defect analysis is performed on the 3x3 NORbased eFlash memory array presented in Figure 4.…”

“…Generally, all reported studies deal with 1T-Flash cells (stacked gate / ETOX) [6,7,8] or 1½TFlash cells (split gate / local SONOS) [6,7,8]. In [1], we have considered the standard 2T-FLOTOX core-cell structure which is now often used in eFlash memories. On the ATMEL 0.15µm eFlash technology, we have performed a qualitative analysis of actual defects which may occur in the memory array.…”

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

“…Up to now, the NOR-based array was preferred to build embedded Flash memories for performance reason, especially the short read access time. Meaningful studies related to electrical simulation models and defect injection for NOR-based array can be found in the literature [3,5,12].…”