An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications

Lin, Yu-Min; Wu, Sheng-Tsai; Shen, Wen-Wei; Huang, Shih-Wei; Kuo, Tzu-Ying; Lin, Ang-Ying; Chang, Tao-Chih; Chang, Hwan‐You; Lee, Shu-Man; Lee, Chia-Hsin; Su, Jay; Liu, Xiao; Wu, Qi; Chen, Kuan‐Neng

doi:10.1109/ectc.2018.00060

Cited by 17 publications

(3 citation statements)

References 9 publications

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“…Lin presented a novel fan-out WLP with the RDL-first method. The FEM was used to optimize the warpage control [68]. Shih introduced an FEM model applied to investigate the thermomechanical properties of a multilayer RDL, finding that a smaller overall size of the fan-out interposer is beneficial in reducing the warpage [69].…”

Section: Current Status Of Reliability Research On Multi-field Coupli...mentioning

confidence: 99%

Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review

Wang,

Liu,

Huo

et al. 2024

Micromachines

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With the advancement of Moore’s Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device’s failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging.

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Section: Current Status Of Reliability Research On Multi-field Coupli...mentioning

confidence: 99%

Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review

Wang,

Liu,

Huo

et al. 2024

Micromachines

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“…[14][15][16] Figure 2 shows a simplified image of the manufacturing process flows: The electrical connections between the die and package are implemented by direct RDL formation on the die pad in a die-first (facedown) process; [17,18] RDL formation is performed after CMP using a die-first (face-up) process; [19,20] and flip chip mounting to RDL is performed using solder bumps on the chip in an RDL-first process. [21,22] In this study, a die-first (face-down) process is selected as the manufacturing process because the corresponding mass production technology has already been established. Unlike other processes, the die-first (face-down) process does not require any components (e.g., Cu pillars, solder bumps) to connect to the RDL, which reduces the manufacturing cost.…”

Section: Issues and Solutions For Fowlpmentioning

confidence: 99%

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

Yamashita

Sekiguchi

2021

Transactions of The Japan Institute of Electronics Packaging

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“…For other chip-last or RDL-first potential applications, see Refs. [93][94][95][96][97][98][99][100][101][102][103].…”

Section: Chip-last or Rdl-first Processmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications

Cited by 17 publications

References 9 publications

Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review

Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

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