An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

Chen, K. M.; Wu, Cheng‐Li; Wang, C. H.; Cheng, Hsien‐Chie; Huang, N. C.

doi:10.1007/s11664-014-3332-x

Cited by 19 publications

(5 citation statements)

References 8 publications

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“…In addition, since the chip is inverted on the solder bumps, thermally conductive silicone grease can be painted on the back of the chip to enhance the heat dissipation capability. Furthermore, removing wire bonding is possible to achieve a higher density layout by redistributing layer (RDL) on the substrate without taking up space on the chip surface [ 13 ]. Hence, the distance between the chip and the substrate is shortened, the time delay of signal transmission is reduced, and the chip performance is improved [ 14 ].…”

Section: Models and Simulationmentioning

confidence: 99%

Reliability Analysis of Flip-Chip Packaging GaN Chip with Nano-Silver Solder BUMP

Liu

et al. 2023

Micromachines

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Gallium nitride (GaN) power devices have many benefits, including high power density, small footprint, high operating voltage, and excellent power gain capability. However, in contrast to silicon carbide (SiC), its performance and reliability can be negatively impacted by its low thermal conductivity, which can cause overheating. Hence, it is necessary to provide a reliable and workable thermal management model. In this paper, a model of a flip-chip packing (FCP) GaN chip was established, and it was assigned to the Ag sinter paste structure. The different solder bumps and under bump metallurgy (UBM) were considered. The results indicated that the FCP GaN chip with underfill was a promising method because it not only reduced the size of the package model but also reduced thermal stress. When the chip was in operation, the thermal stress was about 79 MPa, only 38.77% of the Ag sinter paste structure, lower than any of the GaN chip packaging methods currently in use. Moreover, the thermal condition of the module often has little to do with the material of the UBM. Additionally, nano-silver was found to be the most suitable bump material for FCP GaN chip. Temperature shock experiments were also conducted with different UBM materials when nano-silver was used as bump. It was found that Al as UBM is a more reliable option.

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Section: Models and Simulationmentioning

confidence: 99%

Reliability Analysis of Flip-Chip Packaging GaN Chip with Nano-Silver Solder BUMP

Liu

et al. 2023

Micromachines

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“…(11) Furthermore, the effective Young's modulus (E) and Poisson's ratio (ν) of the Cu 7 In 3 polycrystalline aggregate can be estimated from the calculated polycrystalline bulk and shear moduli, as follows, 9 3 Table 1 presents the predicted bulk modulus, shear modulus, Young's modulus and Poisson's ratio of polycrystalline Cu 7 In 3 . The present calculations agree fairly well with the literature theoretical data [35].…”

Section: A Mechanical Properties and Characteristicsmentioning

confidence: 99%

“…Nevertheless, many critical technical challenges remain to be solved before In-based solders can be successfully implemented. For instance, in flip chip (FC) packaging technology, under bump metallurgy (UBM) that generally involves wetting/seeding, diffusion barrier, adhesion and passivation layers has been commonly exploited as a solid base material for subsequent solder bumping process [7][8][9]. Among the stacked layers in UBM, the seeding layer normally comprises a few micrometer (μm) thick electro-deposited copper.…”

Section: Introductionmentioning

confidence: 99%

First-principles density function calculations of physical properties of triclinic Cu7In3

Cheng

Chen

2016

2016 International Conference on Electronics Packaging (ICEP)

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First principles density functional theory calculations within the generalized gradient approximation are performed to comprehensively study the structural, elastic, electronic and thermodynamic properties of triclinic single and polycrystalline Cu7In3. The polycrystalline elastic properties are predicted using the Voigt-Reuss-Hill approximation and the thermodynamic properties are evaluated based on the quasi-harmonic Debye model. Their temperature, hydrostatic pressure or crystal orientation dependences are also addressed, and the predicted physical properties are compared with the literature experimental and theoretical data and also with those of three other Cu-In compounds, i.e., CuIn, Cu2In and Cu11In9.The present calculations show that in addition to being a much better conductor compared to Cu2In and Cu11In9, Cu7In3 crystal reveals weak elastic anisotropy, high ductility and low stiffness, and tends to become more elastically isotropic at very high hydrostatic pressure. Moreover, the Cu7In3 holds the largest high-temperature heat capacity among the four Cu-In compounds.

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“…For example, interfacial delamination is a problem when Cu pillar bumping is applied on ultralow-K chip. Chen et al (2014) have proposed to use redistribution layer technology to relocate under bump metallurgy pads with aim to reduce the thermalmechanical stress of ultralow-K chip. FEA model was conducted by them to determine the reduction of thermalmechanical stress.…”

Section: Introductionmentioning

confidence: 99%

Influence of copper pillar bump structure on flip chip packaging during reflow soldering: a numerical approach

Ishak

Aziz

Ismail

et al. 2021

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Purpose The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering. Design/methodology/approach In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method. Findings The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation. Practical implications This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process. Originality/value The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

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An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

Cited by 19 publications

References 8 publications

Reliability Analysis of Flip-Chip Packaging GaN Chip with Nano-Silver Solder BUMP

Reliability Analysis of Flip-Chip Packaging GaN Chip with Nano-Silver Solder BUMP

First-principles density function calculations of physical properties of triclinic Cu7In3

Influence of copper pillar bump structure on flip chip packaging during reflow soldering: a numerical approach

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