An SMT-Based Approach to the Formal Analysis of MARTE/CCSL

Formal analysis of functional and non-functional requirements is crucial in automotive systems. The behaviors of those systems often rely on complex dynamics as well as on stochastic behaviors. We have proposed a probabilistic extension of Clock Constraint Specification Language, called PrCCSL, for specification of (non)-functional requirements and proved the correctness of requirements by mapping the semantics of the specifications into UPPAAL models. Previous work is extended in this paper by including an extension of PrCCSL, called PrCCSL * , for specification of stochastic and dynamic system behaviors, as well as complex requirements related to multiple events. To formally analyze the system behaviors/requirements specified in PrCCSL * , the PrCCSL * specifications are translated into stochastic UPPAAL models for formal verification. We implement an automatic translation tool, namely ProTL, which can also perform formal analysis on PrCCSL * specifications using UPPAAL-SMC as an analysis backend. Our approach is demonstrated on two automotive systems case studies.

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“…A3. The detected image should be computed within [20,30]ms in order to generate the desired sign type. A4.…”

Section: Case Studiesmentioning

confidence: 99%

Formal Verification of Dynamic and Stochastic Behaviors for Automotive Systems

Huang

Tian

Kang

2019

2019 24th International Conference on Engineering of Complex Computer Systems (ICECCS)

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“…We present the syntax and semantics of CCSL based on [4,13]. In CCSL, a logical clock actually models a sequence of occurrences of a signal in synchronous models [14].…”

Section: Preliminaries Of Ccsl and Fodlmentioning

confidence: 99%

“…Another subject of analysis for CCSL is to find a schedule of a given CCSL specification [3,13,20], where no system models were involved. The earliest approach [3] combined BDD-based boolean solving and the rewriting on clock expressions, while the method in [20] was based on the rewriting logic in Maude.…”

Section: Related Workmentioning

confidence: 99%

“…The earliest approach [3] combined BDD-based boolean solving and the rewriting on clock expressions, while the method in [20] was based on the rewriting logic in Maude. In [13], the schedule was found by solving an UFLIA formula that encodes the CCSL specification through an SMT-checking procedure. Comparing with [13], we propose a proof system to transform the CDL formula into QF-AFOL formulas, which are more efficient for an SMT-checking procedure to solve.…”

Section: Related Workmentioning

confidence: 99%

“…In [13], the schedule was found by solving an UFLIA formula that encodes the CCSL specification through an SMT-checking procedure. Comparing with [13], we propose a proof system to transform the CDL formula into QF-AFOL formulas, which are more efficient for an SMT-checking procedure to solve.…”

Section: Related Workmentioning

confidence: 99%

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Embedding CCSL into Dynamic Logic: A Logical Approach for the Verification of CCSL Specifications

Zhang¹,

Wu²,

Chen³

et al. 2019

Communications in Computer and Information Science

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The Clock Constraint Specification Language (CCSL) is a clock-based specification language for capturing causal and chronometric constraints between events in Real-Time Embedded Systems (RTESs). Due to the limitations of the existing verification approaches, CCSL lacks a full verification support for 'unsafe CCSL specifications' and a unified proof framework. In this paper, we propose a novel verification approach based on theorem proving and SMT-checking. We firstly build a logic called CCSL Dynamic Logic (CDL), which extends the traditional dynamic logic with 'signals' and 'clock relations' as primitives, and with synchronous execution mechanism for modelling RTESs. Then we propose a sound and relatively complete proof system for CDL to provide the verification support. We show how CDL can be used to capture RTES and verify CCSL specifications by analyzing a simple case study.

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SMT-Based Bounded Schedulability Analysis of the Clock Constraint Specification Language

Zhang

Song

Mallet

et al. 2019

Lecture Notes in Computer Science

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The Clock Constraint Specification Language (CCSL) is a formalism for specifying logical-time constraints on events for the design of real-time embedded systems. A central verification problem of CCSL is to check whether events are schedulable under logical constraints. Although many efforts have been made addressing this problem, the problem is still open. In this paper, we show that the bounded scheduling problem is NP-complete and then propose an efficient SMT-based decision procedure which is sound and complete. Based on this decision procedure, we present a sound algorithm for the general scheduling problem. We implement our algorithm in a prototype tool and illustrate its utility in schedulability analysis in designing real-world systems and automatic proving of algebraic properties of CCSL constraints. Experimental results demonstrate its effectiveness and efficiency.

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An SMT-Based Approach to the Formal Analysis of MARTE/CCSL

Cited by 9 publications

References 14 publications

Formal Verification of Dynamic and Stochastic Behaviors for Automotive Systems

Formal Verification of Dynamic and Stochastic Behaviors for Automotive Systems

Embedding CCSL into Dynamic Logic: A Logical Approach for the Verification of CCSL Specifications

SMT-Based Bounded Schedulability Analysis of the Clock Constraint Specification Language

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