An SOI 4 transistors self-refresh ultra-low-voltage memory cell

Thomas, Olivier; Amara, Ayed Ben

doi:10.1109/iscas.2003.1206296

Cited by 8 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This compares favourably to the balanced transistor where the drive current is the same for both cases. The cells comprising a smaller number of transistors than the classical SRAM cell which has 6 transistors, have been introduced in various technologies to increase the circuit density by suppressing transistors. Among them are the 4T cells which can be classified in two types: * the loadless SRAM: 4T LL in Fig.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

In-depth Analysis of 4T SRAM Cells in Double-Gate CMOS

Giraud

Vladimirescu

Amara

2007

2007 IEEE International Conference on Integrated Circuit Design and Technology

View full text Add to dashboard Cite

This paper presents a whole study of sub-32 nm CMOS 4T SRAM cells in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. Both independent-and connected-gate operation is analyzed either with symmetrical or asymmetrical transistors which have been adjusted according to the current process possibilities.An improved 4T driverless (DL) SRAM cell is proposed and compared with a 4T loadless (LL). Both cells take advantage of the back gate to improve stability in read and retention mode by using a feedback between access transistor and opposite storage node.A set of criteria have been analyzed for an efricient characterization of read-, retention-and write margins, power and access time. Typical and worst cases have been computed to assure operating margins in presence of accurate process variation.

show abstract

Section: Introductionmentioning

confidence: 99%

“…3(b)) presented in [1], * the driverless SRAM: we propose a new architecture ( Fig. 4(d)) taking benefit from the double gate technology by using a feedback and derived from an ultra low voltage partially depleted (PD) SOI transistor presented in [6] (Fig. 4(c)).…”

Section: Introductionmentioning

confidence: 99%

In-depth Analysis of 4T SRAM Cells in Double-Gate CMOS

Giraud

Vladimirescu

Amara

2007

2007 IEEE International Conference on Integrated Circuit Design and Technology

View full text Add to dashboard Cite

show abstract

“…It is for this reason that current sensing circuits are investigated in this paper for an ULV CMOS-SOI SRAM [1]. A current readout circuit is a current buffer shunting the large capacitive reactance of the bitlines by a small input resitance and producing a current signal at its output which is converted to a voltage difference at the output load.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low-Voltage Current-Sense Read Circuits for CMOS SOI SRAMs

Thomas

Vladimirescu

Amara

2005 IEEE International SOI Conference Proceedings

Self Cite

View full text Add to dashboard Cite

For SRAM circuits operated at 0.5V reliable readout of the stored information is challenging due to a voltage swing of tens of mV. Two readout topologies described in this paper for ultra-low-voltage (ULV) SOI-CMOS SRAMs exploit unique features of Partially-Depleted(PD)-SOI transistors to perform current rather than voltage sensing. The analysis presented leads to the dimensioning of the sense amplifier transistors for robust operation with a maximum number of cells per column of the SRAM. Simulations of the presented circuits demonstrate that the information stored in an SRAM with a fourtransistor CMOS-SOI cell can be reliably accessed in 3ns with 180nW power consumption. IntroductionThe low-voltage trend for digital circuits has its roots in the lower power consumption of CMOS logic families operating at lower supply voltages and the proliferation of memory real-estate as a dominant part of the entire chip. The stored charge in each memory cell continues to decrease which raises the need for sense amplifiers very sensitive to reduced swings on the bit lines.Memory readout circuits can sense either a small voltage difference on the bitlines or sense a current difference. Most memories operating under conventional bias use voltage sensing by differential amplifiers or bistable circuits.Memories operated at ULV generate a very small voltage swing which coupled with the high capacitance of the bit lines lead to a very slow and unreliable readout by traditional voltage-sensing circuits. It is for this reason that current sensing circuits are investigated in this paper for an ULV CMOS-SOI SRAM [1]. A current readout circuit is a current buffer shunting the large capacitive reactance of the bitlines by a small input resitance and producing a current signal at its output which is converted to a voltage difference at the output load. The basic concept of a current sense amplifier is a variable-gain current buffer controlled by Vin on the bit line as shown in Fig. 1.

show abstract

Stability analysis of a 400 mV 4-transistor CMOS-SOI SRAM cell operated in subthreshold

Thomas

Amara

Vladimirescu³

2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668)

View full text Add to dashboard Cite

An SOI 4 transistors self-refresh ultra-low-voltage memory cell

Cited by 8 publications

References 11 publications

In-depth Analysis of 4T SRAM Cells in Double-Gate CMOS

In-depth Analysis of 4T SRAM Cells in Double-Gate CMOS

Ultra-Low-Voltage Current-Sense Read Circuits for CMOS SOI SRAMs

Stability analysis of a 400 mV 4-transistor CMOS-SOI SRAM cell operated in subthreshold

Contact Info

Product

Resources

About