Ultra-Low-Voltage Current-Sense Read Circuits for CMOS SOI SRAMs

Abstract

For SRAM circuits operated at 0.5V reliable readout of the stored information is challenging due to a voltage swing of tens of mV. Two readout topologies described in this paper for ultra-low-voltage (ULV) SOI-CMOS SRAMs exploit unique features of Partially-Depleted(PD)-SOI transistors to perform current rather than voltage sensing. The analysis presented leads to the dimensioning of the sense amplifier transistors for robust operation with a maximum number of cells per column of the SRAM. Simulations of the presented circuits demonstrate that the information stored in an SRAM with a fourtransistor CMOS-SOI cell can be reliably accessed in 3ns with 180nW power consumption. IntroductionThe low-voltage trend for digital circuits has its roots in the lower power consumption of CMOS logic families operating at lower supply voltages and the proliferation of memory real-estate as a dominant part of the entire chip. The stored charge in each memory cell continues to decrease which raises the need for sense amplifiers very sensitive to reduced swings on the bit lines.Memory readout circuits can sense either a small voltage difference on the bitlines or sense a current difference. Most memories operating under conventional bias use voltage sensing by differential amplifiers or bistable circuits.Memories operated at ULV generate a very small voltage swing which coupled with the high capacitance of the bit lines lead to a very slow and unreliable readout by traditional voltage-sensing circuits. It is for this reason that current sensing circuits are investigated in this paper for an ULV CMOS-SOI SRAM [1]. A current readout circuit is a current buffer shunting the large capacitive reactance of the bitlines by a small input resitance and producing a current signal at its output which is converted to a voltage difference at the output load. The basic concept of a current sense amplifier is a variable-gain current buffer controlled by Vin on the bit line as shown in Fig. 1.