An Ultra Compact Watt-Level Ka-Band Stacked-FET Power Amplifier

Nguyen, Duy P.; Pham, Anh-Vu

doi:10.1109/lmwc.2016.2574831

Cited by 42 publications

(8 citation statements)

References 8 publications

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“…It was proved that, at such high frequency, this fork structure with underlying gate line is affected by a crosstalk so heavy that it completely hampers the stacking principle of operation. Alternative connection strategies do exist, such as the ones in References 13,16,and 17. The former is claimed to be less affected by crosstalk, as it relies on an asymmetric and unilateral drain‐to‐source connection, which requires no overlapping with the gate line of the CG stage.…”

Section: Stacked Cell Designmentioning

confidence: 99%

“…For the connection of the transistors, a symmetric and compact topology is selected. This topology is known to be affected by some degree of crosstalk, 13,14 which at higher frequency may completely hamper the design. Here, we compare the results from different EM simulation set‐ups with measurements, and we conclude that it is possible to set up EM simulations in a relatively simple way to accurately predict the measured performance and it is possible to design a stacked cell at this frequency with the expected performance, correctly predicting crosstalk and other parasitic effects.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Evaluation of a stacked‐FET cell for high‐frequency applications (invited paper)

Piacibello

Costanzo

Giofrè

et al. 2021

Int J Numerical Modelling

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This paper presents the design, electromagnetic simulation strategies and experimental characterisation of a two‐stage stacked‐FET cell in a 100 nm GaN on Si technology around 18.8 GHz, suited for Ka band satellite downlink applications. A good agreement is found between the electromagnetic simulations and the measured performance on the manufactured prototype, thus demonstrating that a successful voltage combining architecture can be obtained in the frequency range of interest with the selected topology, based on a symmetric fork‐like connection between the transistors. This proves the effectiveness of an appropriate electromagnetic simulation set‐up in correctly predicting the crosstalk, which typically affects this structure, leading to a correct stacking operation.

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Section: Stacked Cell Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Evaluation of a stacked‐FET cell for high‐frequency applications (invited paper)

Piacibello

Costanzo

Giofrè

et al. 2021

Int J Numerical Modelling

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show abstract

“…As discussed before, in the tuned-load case, it is not possible to drive the device at a power level higher than the one selected to size the load (β x ) otherwise the knee-voltage limit would be exceeded. From (28), sizing the optimum load considering square-wave current results in…”

Section: Over-driving (Upper Current Clipping)mentioning

confidence: 99%

“…Once the harmonic components of the (possibly clipped) current and voltage waveforms are known, the design rules for the PA terminations can be derived, according to the specific design target [12][13][14]. In other words, Fourier analysis [2,5] can be exploited for the theoretical analysis of any kind of PA architecture, from classical current-mode tuned-load (TL) PAs [11] to advanced architectures based on waveform engineering [15], like the harmonic tuned PA [16][17][18], the class-J PA [19,20], the class-FPA [21,22], and their variants [23][24][25][26]), on switched device operation, such as class-E [27], on series-power combination (stacked PA) [28][29][30], or finally on the load [31] and supply modulation [32] concepts.…”

Section: Introductionmentioning

confidence: 99%

A Comprehensive Harmonic Analysis of Current-Mode Power Amplifiers

2021

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This work presents a comprehensive theoretical analysis of current-mode power amplifiers as a function of input power for different biasing classes under the common simplifying assumption of constant transconductance and hard current cut-off/saturation. Typically, the theoretical analysis of power amplifier performance and behavior are carried out only at maximum output power. However, to achieve high data-rates, modern telecommunication systems adopt signals characterized by a very high peak-to-average power ratio, thus it is useful to analyze the power amplifier behavior as a function of power back-off. Moreover, in many cases, to enhance the efficiency and/or to apply harmonic shaping techniques, a clipped drain-source current, which approaches a square wave, is required. The classical analysis can be extended to low power levels only under the assumption of power-independent conduction angle, which is true only for class-A and class-B amplifiers, and does not take into account possible waveform clipping at maximum current. This work presents a complete theoretical Fourier analysis of FET-based power amplifiers as a function of quiescent drain-source current at any input power level and accounting for the clipped current case, up to the square-wave limit, reorganizing and completing the material that can be found in classical textbooks in the field.

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“…In the literature, stacked PAs are largely exploited in CMOS technology [11][12][13][14][15][16][17][18], where the breakdown voltage is a major limit, but some examples can also be found in GaAs [19][20][21][22][23][24][25][26][27] and very few in GaN [28][29][30][31]. A main advantage of the stacked PA is that it can be profitably adopted as a basic high-power and high-gain cell to be further exploited in more complex PA architectures, from classical parallel combined PAs [32] to advanced architectures such as distributed PAs [33], spatially-combined PAs [34] and Doherty PAs [30,35].…”

Section: Introductionmentioning

confidence: 99%

Space-Compliant Design of a Millimeter-Wave GaN-on-Si Stacked Power Amplifier Cell through Electro-Magnetic and Thermal Simulations

et al. 2021

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The stacked power amplifier is a widely adopted solution in CMOS technology to overcome breakdown limits. Its application to compound semiconductor technology is instead rather limited especially at very high frequency, where device parasitic reactances make the design extremely challenging, and in gallium nitride technology, which already offers high breakdown voltages. Indeed, the stacked topology can also be advantageous in such scenarios as it can enhance gain and chip compactness. Moreover, the higher supply voltages and lower supply currents beneficially impact on reliability, thus making the stacked configuration an attractive solution for space applications. This paper details the design of two stacked cells, differing in their inter-stage matching strategy, conceived for space applications at Ka-band in 100 nm GaN-on-Si technology. In particular, the design challenges related to the thermal constraints posed by space reliability and to the electro-magnetic cross-talk issues that may arise at millimeter-wave frequencies are discussed. The best cell achieves at saturation, in simulation, 3 W of output power at 36 GHz with associated gain and efficiency in excess of 7 dB and 35%, respectively.

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An Ultra Compact Watt-Level Ka-Band Stacked-FET Power Amplifier

Cited by 42 publications

References 8 publications

Evaluation of a stacked‐FET cell for high‐frequency applications (invited paper)

Evaluation of a stacked‐FET cell for high‐frequency applications (invited paper)

A Comprehensive Harmonic Analysis of Current-Mode Power Amplifiers

Space-Compliant Design of a Millimeter-Wave GaN-on-Si Stacked Power Amplifier Cell through Electro-Magnetic and Thermal Simulations

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