An Ultra-Efficient Approximate Multiplier With Error Compensation for Error-Resilient Applications

Sabetzadeh, Farnaz; Moaiyeri, Mohammad Hossein; Ahmadinejad, Mohammad

doi:10.1109/tcsii.2022.3215065

Cited by 23 publications

(7 citation statements)

References 21 publications

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“…Similarly, design 2 and design 3 performed well in terms of area, except for[11] and[7] [11]. Regarding power, when compared to imprecise models in the current research landscape, design 2 and design 3 outperformed most, except for[12] D 2 ,[13], and[11],[12] D 2 ,[13], respectively. However, it's worth noting that the research papers[12] D 2 ,…”

mentioning

confidence: 89%

“…Verilog programming language served as the foundation for both the existing and proposed approximate multipliers. [11], and [13] suffer from accuracy issues. Moreover, the proposed model 1 exhibits an impressive 63.01% improvement in ADP (Area-Delay Product) when contrasted with the exact multiplier.…”

Section: Hardware Realizationmentioning

confidence: 99%

“…Validation using image sharpening and image multiplication applications indicates that the suggested designs offer a better balance between performance and image quality. Additionally, it's worth noting that several imprecise multiplier structures have been developed for image filtering [12], edge detection [13], and neural network applications [14]. These structures offer versatile solutions to enhance performance across various domains.…”

Section: Introductionmentioning

confidence: 99%

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Developing and Assessinginexact Multiplierarchitectures for Imageprocessing

Anguraj,

Krishnan

2024

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In the realm of approximate computing, the inexact multiplier architecture stands out as a cornerstone, playing a pivotal role acrosserror-tolerated applications. This article delves into the intricacies ofthree distinct inexact multiplier architectures tailored specifically forimage processing tasks. The study revolves around efficiently partitioning the partial product stage into smaller modules and thenemploying decoder algorithms/truncation techniques, to obtain thesuggested multiplier’s final result. The resulting 8×8 imprecise multipliers are engineered with reduced design overhead and reasonableerror metrics. Through simulation with the Cadence RTL compilerusing TSMC 90 nm technology, the realization showcases substantialarea and power savings compared to conventional imprecise multipliers. Comparing one of the proposed approximate models to precisemultipliers reveals significant reductions in both the area and thepower requirement, amounting to 37.19% and 46.14%, respectively, allwhile ensuring acceptable error metrics. Furthermore, in comparison toalternative approximation multiplier designs, the suggested 8×8 multiplier showcases superior performance metrics. It achieves justifiablemean Structural Similarity Index (SSI) values, making it particularlyadvantageous for tasks such as picture multiplication and sharpening.

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mentioning

confidence: 89%

Section: Hardware Realizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Developing and Assessinginexact Multiplierarchitectures for Imageprocessing

Anguraj,

Krishnan

2024

Preprint

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“…(3) Fast addition (carry propagation) of two operands which produces the final result [2]. The partial products reduction phase in a parallel multiplier consumes the most power dissipation, delay, and area of a multiplier.…”

Section: Introductionmentioning

confidence: 99%

“…The partial products reduction phase in a parallel multiplier consumes the most power dissipation, delay, and area of a multiplier. Therefore, compressor circuits play a constructive role in the efficiency of a fast multiplier, and many other arithmetic designs [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Noise and PVT Tolerant, High-Speed and Energy-Efficient Hybrid 4-2 Compressor in CNFET Technology

Maleknejad

Sharifi

2023

Preprint

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In this paper, a novel high-speed and energy efficient 4 − 2 compressor cell is proposed using Carbon Nanotube Field Effect Transistors (CNFETs). The proposed compressor is realized efficiently based on NAND-NOR gates and multiplexers. To estimate the performance of the presented design, simulations are carried out using Synopsis HSPICE under different conditions. The results demonstrate the performance improvement of the proposed design compared to the best reference designs in terms of delay and energy consumption, by 20 and 26%, respectively. Also, the susceptibility of the proposed design against the process, voltage, temperature (PVT), and noise variations is examined. It is robust against PVT variations and high amplitude of noises compared with its counterpart. Also, it displays the most robustness, in terms of PVT variations compared with its counterpart. Furthermore, it has the best results in large structures, such as a multiplayer. Furthermore, embedding the proposed compressor in an 8× 8-bit binary multiplier demonstrates that it has better speed and PDP with regard to its counterparts.

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