An ultra-low-power CMOS on-chip interconnect architecture

Bellaouar, A.; Abu-Khater, Issam S.; Elmasry, M.I.

doi:10.1109/lpe.1995.482461

“…VLSI design for power optimization to satisfy the power budget is an important research issue [2]. We can split the bus topology into different segments to reduce the power consumption [4,12].…”

Section: Related Workmentioning

confidence: 99%

Handbook of Software Engineering

Vick

¹

,

Ramamoorthy

²

2019

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As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should possibly match communication workflows among these components. In this paper, we first propose an interconnection architecture for SoC, which uses crossroad switches to construct a dedicated communication path dynamically between any two cores. We then present a design methodology for constructing network on chip (NoC) for application-specific computer systems with profiled communication characteristics. We design a core placement tool, which automatically maps cores to a communication topology such that we can minimize the total communication energy. Experimental results show that the design methodology can generate optimized on-chip networks with fewer resources than meshes and tori, and the power saving approximates to 40%.

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“…The Communication Distance (CDist) between two switches si, sj , denoted CDist(T , si, sj), on a switch topology tree T is the number of switch hops and edges traversed from si to sj on T , where CDist(T, si, sj) = e∈P aths i ,s j EL bit + switch∈P aths i ,s j ES bit(2) …”

mentioning

confidence: 99%

A low-power crossroad switch architecture and its core placement for network-on-chip

Chang

¹

,

Shen

²

,

Chen

³

2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should possibly match communication workflows among these components. In this paper, we first propose an interconnection architecture for SoC, which uses crossroad switches to construct a dedicated communication path dynamically between any two cores. We then present a design methodology for constructing network on chip (NoC) for application-specific computer systems with profiled communication characteristics. We design a core placement tool, which automatically maps cores to a communication topology such that we can minimize the total communication energy. Experimental results show that the design methodology can generate optimized on-chip networks with fewer resources than meshes and tori, and the power saving approximates to 40%.

show abstract