An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio

Cohen, E.; Ravid, Shmuel; Ritter, D.

doi:10.1109/rfic.2008.4561386

Cited by 54 publications

(40 citation statements)

References 4 publications

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“…The effect of the gate-drain capacitance C gd1 of the input transistor M 1 on the input impedance can be modeled by the Miller capacitance C miller given by (2).…”

Section: Input Impedance Matchingmentioning

confidence: 99%

“…Taking into account of typical inductance values, the transistor width is about 30-40 µm at 60 GHz [2]. In this paper, transistor width is designed to be 30 µm and the input inductance is about 80 pH.…”

Section: Drain Current Optimizationmentioning

confidence: 99%

“…In the last few years, an unlicensed frequency band ranging from 57 to 64 GHz has attracted great attention, which offers much wider bandwidth and less potential interferes [2,4,9]. Many CMOS circuits and sub-systems designed for this band have been reported in recent literatures [2][3][4]8,9].…”

Section: Introductionmentioning

confidence: 99%

“…Many CMOS circuits and sub-systems designed for this band have been reported in recent literatures [2][3][4]8,9]. However, the design of low cost and highperformance RF circuits and systems within this frequency range is still challenging.…”

Section: Introductionmentioning

confidence: 99%

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A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

Feng

et al. 2015

Circuits Syst Signal Process

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In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a currentreused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the currentreused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum S 21 gain of 11.4 dB gain with a −3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the Circuits Syst Signal Process measured S 11 and S 12 are less than −10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.

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“…The effect of the gate-drain capacitance C gd1 of the input transistor M 1 on the input impedance can be modeled by the Miller capacitance C miller given by (2).…”

Section: Input Impedance Matchingmentioning

confidence: 99%

Section: Drain Current Optimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

Feng

et al. 2015

Circuits Syst Signal Process

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show abstract

“…The total power consumption is 30 mW, since 26 mA from V G ¼ 700 mV and 10 mA from V DD ¼ 1.2 V are drawn. Table 1 shows the comparison between the measured performance of the presented design and the other recently published 60 GHz 90 nm CMOS LNAs ( [10][11][12][13][14][15]). It can be seen as our design is in line with the state of the art in LNA design.…”

Section: V M E a S U R E M E N T S V E R S U S S I M U L A T I O N Smentioning

confidence: 99%

A 60 GHz fully differential LNA in 90 nm CMOS technology

Malignaggi

Hamidian

Boeck

2013

Int. j. microw. wirel. technol.

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The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm 2 pads included. The detailed design procedure and the achieved measurement results are presented in this work.

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60GHz Radio Implementation in Silicon

Valdes‐Garcia

2010

60 GHz Technology for GBPS WLAN and WPAN

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An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio

Cited by 54 publications

References 4 publications

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

A 60 GHz fully differential LNA in 90 nm CMOS technology

60GHz Radio Implementation in Silicon

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