An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications

Pereira, M. Silva; Vaz, J. Caldinhas; Leme, C.A.; Sousa, J.T. de; Freire, J. Costa

doi:10.1109/iscas.2015.7168861

Cited by 4 publications

(1 citation statement)

References 11 publications

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“…This wide variation in the exponent will cause, in turn, a huge variation in the CER value, which goes from 10 -258 to 10 -9 . Even so, the obtained CERs are compatible with the necessary Bit Error Rate (BER) reported in the literature for low power Zigbee and BLE frontends [19,20], ranging from 10 -6 up to 10 -3 . For more strict applications, the CER of the ADC can be greatly reduced by limiting the supply voltage to V DD ± 5%.…”

Section: Simulation Resultssupporting

confidence: 81%

A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS

Campos

Navarro

Luppe

et al. 2021

Analog Integr Circ Sig Process

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During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 mm2.

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Section: Simulation Resultssupporting

confidence: 81%