An ultra-low power redundant split-DAC SA-ADC using power-optimized programmable comparator

Abstract

An ultra-low power successive approximation (SA) analog-to-digital converter (ADC) based on the redundant search algorithm is proposed. The power consumption of the comparator is significantly reduced through gain control of the preamplifier during conversion phase. The number of analog sampling switches is reduced to one by introducing modified clock boosting switch. A single-ended 8-bit SA-ADC is designed in a 0.18 µm CMOS process. Our simulation results show that at a supply voltage of 0.9 V and an output rate of 500 kS/s, the SA-ADC achieves a peak signal-to-noise-and-distortion (SNDR) ratio of 48 dB, and a power consumption of 1.63 µW, resulting in a figure of merit of 15.9 fJ/conversion-step.

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

“…Another technique is known as a generalized non-binary algorithm, where a non-integer ratio of capacitances is not needed [33], [43], [45][46][47], [52], [54], [58], [59], [61], [63], [65], [69]. For example, a non-binary weight such as {128, 46,26,20,14,8,6,4,2,1} instead of the binary weight of {128, 64,32,16,8,4,2,1} was used to obtain 8-bit resolution [69].…”