An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

Abstract

This paper presents a 0.55 V, 7 bit, 160 MS/s pipeline ADC using dynamic amplifiers. In this ADC, high-speed open-loop dynamic amplifiers with a common-mode detection technique are used as residue amplifiers to increase the ADC's speed, to enhance the robustness against supply voltage scaling, and to realize clockscalable power consumption. To mitigate the absolute gain constraint of the residue amplifiers in a pipeline ADC, the interpolated pipeline architecture is employed to shift the gain requirement from absolute to relative accuracy. To show the new requirements of the residue amplifiers, the effects of gain mismatch and nonlinearity of the dynamic amplifiers are analyzed. The 7 bit prototype ADC fabricated in 90 nm CMOS demonstrates an ENOB of 6.0 bits at a conversion rate of 160 MS/s with an input close to the Nyquist frequency. At this conversion rate, it consumes 2.43 mW from a 0.55 V supply. The resulting FoM of the ADC is 240 fJ/conversion-step.

High‐gain and power‐efficient dynamic amplifier for pipelined SAR ADCs

“…As shown in Fig. 3 b , the CM voltage of both outputs is sensed by two inverters, the outputs of which are shorted [3]. Once the voltage on node surpasses the threshold of the following inverter, goes low, the output switches S p , S n are switched off and the output voltage is frozen to a steady state.…”

“…Traditional continuous‐time amplifiers used in switched‐capacitor circuits have a key limitation that is the high power consumption. However, by substituting the continuous‐time current with a discrete‐time current, dynamic amplifiers are able to achieve low power while maintaining excellent performance [1–3]. Unfortunately, the gain and noise performances of the conventional dynamic amplifier are limited by the ratio in a certain CMOS technology [1].…”

“…By having a complementary input and a reference level detector (RLD), a high gain, LNA is made possible. The proposed amplifier consumes less energy than other dynamic amplifiers [1][2][3][4][5], resulting in an improvement of the pipelined SAR ADC efficiency.…”

0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control

“…These include subthreshold-operated MOS transistors [1,2], bulk (body) driven [3,4], floating gate and quasi-floating gate MOS transistors [5,6], threshold lowering [7,8], level shifting [9], complementary pairs with body-driven gain boosting, and non-tailed pairs [10]. Additional approaches have also been proposed to replace OTAs, though not for general purpose usage, including dynamic amplifiers [11], ring amplifiers [12], and zero-crossing based circuits [13]. In addition, one interesting trend is the use of inverter-based topologies [14][15][16][17][18][19][20][21][22][23][24][25][26][27][28].…”

Design and Analysis of 0.5-<inline-formula> <tex-math notation="LaTeX">$f_{\mathrm{T}}$ </tex-math> </inline-formula> Bandwidth THAs With Resolution Enhancement Techniques in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m SiGe Process

“…processing. Successive approximation register (SAR) [1]- [3] and pipeline [4]- [6] ADCs are appropriate candidates for high-resolution calculations of 10-14 bits. However, their sampling speed is restricted because they use digital-to-analog convertors, which are difficult to design up to the MMW band.…”