An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique

Wang, Chao; Ji, Yingchun; Ma, Ce; Cai, Qiao; Qi, Liang; Li, Yongfu

doi:10.1109/access.2021.3077090

Cited by 8 publications

(3 citation statements)

References 24 publications

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“…[9], TVLSI'17 0.20-1.10 40 11.57 (@0.4, 1.0) 67.4f (@0. which shows that the circuit provides good performance at lower conversion gain (converting 1.6 to 3 V). Designing circuits to work in subthreshold is essential for low-power budget applications, such as in biomedical implants [46]- [49]. The results in Fig.…”

Section: B Simulated Performancementioning

confidence: 99%

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

et al. 2022

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A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 µm CMOS technology occupies a silicon area of only 25 µm×25 µm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, VDDL=0.8 V, and a capacitive load of CL=0.1 pF.

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Section: B Simulated Performancementioning

confidence: 99%

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

et al. 2022

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“…The level converter exhibits the ability to convert a signal with an initial voltage of 1.2 V. The delay of this level converter is measured to be 17.86 ns, while its power consumption remains constant at 73.95 pW. Furthermore, numerous alternative low-voltage LS designs have been presented in the literature [9][10][11] as potential solutions for the implementation of energy-efficient pull-down and pull-up systems [12][13][14].…”

Section: Introduction and Literature Surveymentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

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“…In addition, based on a periodically‐refreshed charge pump circuit, Palomeque‐Mangut et al 21 exhibit a high‐voltage floating LS, which slides digital signals by varying the low supply rail from ground to VSSH while preserving the input signal swing. Wang et al 22 show a multi‐function ultra‐low‐voltage LS with re‐configurable logic with embedded time‐borrowing latch. The LS presented in Kim et al 23 removes the static current with a cut‐off head PMOS, of which the contention between the pull‐up and pull‐down networks at the internal node is reduced by using a ‘low’ to ‘high’ transition error correction circuit.…”

Section: Introductionmentioning

confidence: 99%

An energy‐efficient level shifter based on a differential cascade voltage switch structure

Zhang

Liu

et al. 2022

Circuit Theory & Apps

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Based on differential cascade voltage switch architecture, this paper proposes a level shifter with optimized energy consumption, constructed by stacking diode‐connected NMOS and PMOS transistors and splitting input signals of the two output stages. Eventually, the overlap time of input signals of the two output stages has been reduced, during which there is a considerable short‐current from high voltage source to ground. When implemented in a 110 nm CMOS process, post‐layout netlist simulations show that the proposed level shifter exhibits a 2.31 ns switching delay and 819 fJ energy consumption when converting a 1.5 V input signal into 4.5 V with 10 MHz operational frequency and 15 fF output load.

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An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique

Cited by 8 publications

References 24 publications

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

An energy‐efficient level shifter based on a differential cascade voltage switch structure

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