An ultra-thin interposer utilizing 3D TSV technology

Heterogeneous 2.5D integration on through silicon interposer

“…Introduction A typical 2.5D interposer package consists of one or multiple guest dies stacked on top of a thinned TSV interposer, which is in turn assembled on either an organic flip chip BGA (FCBGA) or a ceramic substrate. [75][76][77][78][79] Figure 33 shows an example of a 2.5D interposer package. The two guest chips could be assembled side-by-side on the interposer as shown in the schematics or be replaced by one or more stacks of multiple dies (for example, memory cube).…”

“…The CoW-first assembly flow integrates the TSV wafer processing with guest chip attach before completion of the TSI wafer fabrication and is known as chip-on-wafer-onsubstrate (CoWoS). [77][78][79] Section III B 3 describes the CoWoS process and an example of the assembled package. 1.…”

“…In this CoW-first assembly flow, [77][78][79] the guest dies are flip-chip bonded on TSI wafer after the completion of TSV formation, front-side multi-layer interconnect, and front-side micro-bump formation, but before back-side wafer thinning and TSV reveal during the TSI wafer fabrication. After the completion of guest chips attach, the CoW wafer is molded and thinned down to 100 lm or less from the backside to reveal the TSV and is followed by C4 bumping process before it is singulated into individual "CoW" dies for assembly onto substrate to complete the CoWoS process flow.…”

“…After the completion of guest chips attach, the CoW wafer is molded and thinned down to 100 lm or less from the backside to reveal the TSV and is followed by C4 bumping process before it is singulated into individual "CoW" dies for assembly onto substrate to complete the CoWoS process flow. This CoW-first assembly flow is heavily promoted by TSMC and is called CoWoS [77][78][79] technology. The schematics of the CoWoS process flow are shown in Figure 36.…”

Bonding technologies for chip level and wafer level 3D integration

“…Some key technologies needed to enable 3Di include the formation of through-silicon-vias (TSV), wafer bonding and wafer thinning. 3D integration can include a Si interposer, which is used to redirect circuitry between a chip carrier and one or more top chips [4,5]. High-precision alignment, positioning and bonding are required for the fabrication of various 3Di devices, especially for fine-pitch 3D.…”