An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage

Qu, Xi; Zhou, Zekun; Zhang, Bo; Li, Zhaoji

doi:10.1109/tcsii.2012.2235732

Cited by 72 publications

(44 citation statements)

References 11 publications

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“…The design of LDO starts with the design of pass element since it decides many vital performance parameters of LDO [1]. The pass element can be realized using Darlington pair, JFETs or MOSFETs.…”

Section: Fig1 Typical Architecture Of Ldomentioning

confidence: 99%

Untitled

2016

IJME

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This paper illustrates the design and implementation of a Low Drop out voltage regulator which consumes low power and occupies less area. The regulator uses single stage error amplifier hence area consuming compensation capacitor is avoided. It needs only 16μA quiescent current making it suitable for low power applications. The proposed regulator has been designed in 180nm CMOS technology and performance is tested using spice tool and layout is done using MAGIC VLSI tool. Simulation results show that the LDO has a line regulation of 0.001V/V and load regulation of 0.002V/mA. The LDO occupies an area of 70μm × 80μm and power dissipation is 20μW.

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Section: Fig1 Typical Architecture Of Ldomentioning

confidence: 99%

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2016

IJME

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“…Adaptive biasing circuit, which sources a fraction of the load current (I L ) to boost the bias current at heavy load, is widely used in the on-chip LDO design [3,4]. With the help of adaptive biasing circuit, the transient performances of the LDO could be enhanced significantly without increasing the I Q at light load.…”

Section: Introductionmentioning

confidence: 99%

A low-power on-chip LDO with advanced reference buffer

Zhou

Zhang

2014

IEICE Electron. Express

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A low-power fast-transient on-chip low-dropout regulator (LDO) using advanced reference buffer is presented in this paper. The advanced reference buffer is proposed to provide the reference voltage of the LDO with more accurate level to improve the regulation performances. Moreover, in order to suppress the undershoot, the advanced reference buffer increases the reference voltage of the LDO abruptly when the output voltage decreases during transient state. Hspice simulation results show that the proposed LDO could deliver 100-mA load current with 0.8-V output voltage and 200-mV dropout voltage. By only consuming 1.8-µA quiescent current at light load, the undershoot, the overshoot and the settling time of the proposed LDO for load current switching from 100 µA to 100 mA with 300-ns edge time are about 60 mV, 80 mV and 1 µs, respectively.

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“…On-chip low-dropout regulators (LDOs) are widely used in mobile systems due to the low-noise characteristics and few external components [1,2]. Since there is no large load capacitor (C L Þ to absorb the output voltage (V OUT ) spike, the transient response of the on-chip LDO is very crucial.…”

Section: Introductionmentioning

confidence: 99%

“…Consequently, the phase margin is reduced when the load current (I L ) is low. Hence, area-consuming Miller capacitors, which degrade the SR G , are inevitably used to reduce the GBW to ensure the stability [1]. Then both the size of the LDO and the quiescent current (I Q ) are increased.…”

Section: Introductionmentioning

confidence: 99%

“…The proposed ADB circuit is composed of advanced dynamic biasing current generator (ADBCG) and a related slew rate enhancement (SRE) circuit. To improve the driven ability of amplifier with low I Q , a class-AB amplifier based on flipped voltage follower [1,4] is utilized. Then the ADBCG couples the output voltage spike directly [3] to boost the bias current of the on-chip LDO during transient state and maintains low I Q in steady state.…”

Section: Introductionmentioning

confidence: 99%

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A fast-transient on-chip LDO with advanced dynamic biasing circuit

Zhou

Zhang

et al. 2014

IEICE Electron. Express

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A low-power fast-transient on-chip low-dropout regulator (LDO) using advanced dynamic biasing circuit is presented in this paper. The proposed advanced dynamic biasing circuit is composed of an advanced dynamic biasing current generator and a related slew rate enhancement circuit. The advanced dynamic biasing current generator boosts the bias current of the LDO momentarily during the transient state through coupling the output voltage spike. In addition, the slew rate enhancement circuit, which utilizes the dynamic biasing current, suppresses the output voltage spike with an automatic on/off feature. From the Hspice simulation results, the output voltage is regulated at 0.8 V from a 1-V supply voltage. The output voltage recovers within 1.4 µs at a voltage spike less than 80 mV for load current switching from 50 µA to 100 mA with 300-ns rise and fall time.

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An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage

Cited by 72 publications

References 11 publications

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A low-power on-chip LDO with advanced reference buffer

A fast-transient on-chip LDO with advanced dynamic biasing circuit

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