An upper bound for 3D slicing floorplans

Salewski, Silke; Barke, Erich

doi:10.1109/aspdac.2002.994982

Cited by 10 publications

(2 citation statements)

References 25 publications

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“…FLOORPLANING AND PLACE&ROUT There are two differe c approaches to l rp 3D systems. On one hand, there are stochastic methods l ulated annealing [11,12], genetic algorithms [13] or threshold accepting. On the other hand, analytical approaches are used which apply, for example, a force model [14].…”

Section: D Data Structuresmentioning

confidence: 99%

Integration of multi physics modeling of 3D stacks into modern 3D data structures

Schneider

Heinig

Fischbach

et al. 2010

2010 IEEE International 3D Systems Integration Conference (3DIC)

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Abstract-This paper deals with the concept of how to integrate results of multi physics investigation of 3D stacks into modern comprehensive 3D data structures. Beside a description of modern 3D data structures and methods for floorplanning and Place&Route, approaches for multi physics modeling are introduced. The extension of the layout optimization process by multi physics modeling is investigated. Finally, we conclude with a summary of the future needs for an improved interoperability.

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Section: D Data Structuresmentioning

confidence: 99%

Integration of multi physics modeling of 3D stacks into modern 3D data structures

Schneider

Heinig

Fischbach

et al. 2010

2010 IEEE International 3D Systems Integration Conference (3DIC)

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“…Silke [4] presented an upper bound for the volume of slicing floorplans. Fekete and Teich [5] [6] proposed an enumeration scheme by using a branch and bound tree search algorithm to find a feasible solution.…”

Section: Introductionmentioning

confidence: 99%

Cubic Packing with Various Candidates for 3D IC Design

Hong

et al. 2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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In this paper, we introduce various candidates for circuit blocks so that the floorplanner can dynamically choose the implementations of blocks to optimize the whole chip. Especially in 3D IC deign, some components may occupy more than one layers, we propose a novel method to optimize the cubic packing with various candidates. Based on 3D-CBL( 3-Dimensional Corner Block List) representation, we can handle the layer number constraints heuristically and we guarantee the feasibility of the final results. Experimental results show that our algorithm is effective and efficient.

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